Inventor
KOCH GARRETT STEPHEN
US10 patents
Patents
10 patentsUS5859804AJan 12, 1999
Method and apparatus for real time two dimensional redundancy allocation
IBM119 citations97
US6026505AFeb 15, 2000
Method and apparatus for real time two dimensional redundancy allocation
IBM55 citations95
US5790564AAug 4, 1998
Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor
IBM25 citations92
US5784323AJul 21, 1998
Test converage of embedded memories on semiconductor substrates
IBM50 citations89
US5771242AJun 23, 1998
Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor
IBM12 citations73
US5761213AJun 2, 1998
Method and apparatus to determine erroneous value in memory cells using data compression
IBM11 citations73
US5745498AApr 28, 1998
Rapid compare of two binary numbers
IBM8 citations73
US5918003AJun 29, 1999
Enhanced built-in self-test circuit and method
IBM12 citations68
US8006153B2Aug 23, 2011
Multiple uses for BIST test latches
IBM5 citations59
US7574642B2Aug 11, 2009
Multiple uses for BIST test latches
IBM4 citations59