Inventor

SCHOELLKOPF JEAN-PIERRE

FR28 patents

⚠️ This page may combine multiple inventors who share the name “SCHOELLKOPF JEAN-PIERRE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHOELLKOPF JEAN-PIERRE

ST MICROELECTRONICS SA

One-time programmable memory cell in CMOS technology

Method of making an electrically programmable memory cell

Semiconductor test structure formed in cutting path of semiconductor water

Memory circuit comprising an error correcting code

Parity checking circuit

Read only memory integrated semiconductor device

Process for producing a resistor in an integrated circuit and corresponding integrated static random access memory device having four transistors and two resistors

MOS memory point

Circuit for validating simulation models

Embedded capacitor

One-time programmable memory device

SRAM memory device with flash clear and corresponding flash clear method

Programmable non-volatile memory device and method of programming the same

Storage element with a defined number of write cycles

Electrically programmable memory cell

Semiconductor device having several assembled integrated-circuit chips and method of assembling and electrically connecting the integrated-circuit chips

Integrated circuit power supply network

Semiconductor memory device and corresponding programming method

Fast memory circuits and methods

High density integrated read-only memory (ROM) with reduced access time

Method of repairing an integrated electronic circuit using a formed electrical isolation

SGS THOMSON MICROELECTRONICS

Device for checking the skew between two clock signals

Circuit indicating the phase relation between several signals having the same frequency

Latch operating with a low swing clock signal

BULL SA

Bus control device comprising a plurality of isolatable segments

Sense amplifier with bit-line derived clocking

SGS THOMSON MICROELECTRONIS S A

Method of accurate simulation of logic circuits

FIRMIN FABIAN

Flip-flop with single clock phase and with reduced dynamic power