Inventor

KAI JAMES K

US34 patents

⚠️ This page may combine multiple inventors who share the name “KAI JAMES K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAI JAMES K

ADVANCED MICRO DEVICES INC

Dual damascene process using sacrificial spin-on materials

Low K dielectic etch in high density plasma etcher

Dual damascene process using sacrificial spin-on materials

Integration of organic fill for dual damascene process

In-situ etch of BARC layer during formation of local interconnects

Fluted via formation for superior metal step coverage

Fluted via formation for superior metal step coverage

Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning

In-situ etch of multiple layers during formation of local interconnects

SANDISK TECHNOLOGIES INC

Three dimensional NAND device with birds beak containing floating gates and method of making thereof

3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same

Integrated nanostructure-based non-volatile memory fabrication

Three dimensional NAND device with birds beak containing floating gates and method of making thereof

Nanodot enhanced hybrid floating gate for non-volatile memory devices

Integrated nanostructure-based non-volatile memory fabrication

Metal control gate structures and air gap isolation in non-volatile memory

Semiconductor device with copper interconnects separated by air gaps

SILICON GENESIS CORP

Nozzle for cleaving substrates

Substrate cleaving tool and method

Nozzle for cleaving substrates

Substrate cleaving tool and method

SANDISK 3D LLC

Resistance-switching memory cell with multiple raised structures in a bottom electrode

Resistance-switching memory cell with multiple raised structures in a bottom electrode

Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask

Process for forming resistive switching memory cells using nano-particles

PURAYATH VINOD ROBERT

Metal control gate structures and air gap isolation in non-volatile memory

Method for forming self-aligned dielectric cap above floating gate

SANDISK CORP

Dielectric layer above floating gate for reducing leakage current

Method of forming dielectric layer above floating gate for reducing leakage current

MATAMIS GEORGE

Self-aligned three-dimensional non-volatile memory fabrication

PURAYATH VINOD R

Copper interconnects separated by air gaps and method of making thereof

SANDISK TECHNOLOGIES LLC

Preventing erase disturb in NAND

KAI JAMES K

Non-volatile memory cell containing a nano-rail electrode