Inventor

MANLEY DWIGHT P

US15 patents

⚠️ This page may combine multiple inventors who share the name “MANLEY DWIGHT P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIGITAL EQUIPMENT CORP

10 patents

US4888679ADec 19, 1989

Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements

DIGITAL EQUIPMENT CORP151 citations99

US5142634AAug 25, 1992

Branch prediction

DIGITAL EQUIPMENT CORP276 citations97

US4985825AJan 15, 1991

System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer

DIGITAL EQUIPMENT CORP128 citations97

US5222223AJun 22, 1993

Method and apparatus for ordering and queueing multiple memory requests

DIGITAL EQUIPMENT CORP100 citations96

US5113515AMay 12, 1992

Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer

DIGITAL EQUIPMENT CORP67 citations95

US5109495AApr 28, 1992

Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor

DIGITAL EQUIPMENT CORP105 citations94

US5349651ASep 20, 1994

System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation

DIGITAL EQUIPMENT CORP51 citations92

US5168573ADec 1, 1992

Memory device for storing vector registers

DIGITAL EQUIPMENT CORP41 citations90

US5142631AAug 25, 1992

System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register

DIGITAL EQUIPMENT CORP54 citations90

US5019965AMay 28, 1991

Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width

DIGITAL EQUIPMENT CORP28 citations90

INTEL CORP

4 patents

US11693691B2Jul 4, 2023

DIGITAL EQUIPMENT

1 patent

US4980817ADec 25, 1990

Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports

DIGITAL EQUIPMENT42 citations90

MANLEY DWIGHT P

DIGITAL EQUIPMENT CORP

Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements

Branch prediction

System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer

Method and apparatus for ordering and queueing multiple memory requests

Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer

Method and apparatus using a source operand list and a source operand pointer queue between the execution unit and the instruction decoding and operand processing units of a pipelined data processor

System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation

Memory device for storing vector registers

System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register

Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width

INTEL CORP

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

DIGITAL EQUIPMENT

Vector register system for executing plural read/write commands concurrently and independently routing data to plural read/write ports