Inventor

RIVOIR JOCHEN

US50 patents

⚠️ This page may combine multiple inventors who share the name “RIVOIR JOCHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RIVOIR JOCHEN

RIVOIR JOCHEN

Re-configurable test circuit, method for operating an automated test equipment, apparatus, method and computer program for setting up an automated test equipment

Decorrelation of data by using this data

Data processing unit and a method of processing data

Format transformation of test data

Calibrating signals by time adjustment

Method of sharing a test resource at a plurality of test sites, automated test equipment, handler for loading and unloading devices to be tested and test system

Apparatus and method for wireless testing of a plurality of transmit paths and a plurality of receive paths of an electronic device

Apparatus and method for estimating data relating to a time difference and apparatus and method for calibrating a delay line

Method and apparatus for determining relevance values for a detection of a fault on a chip and for determining a fault probability of a location on a chip

Analog signal generation using a delta-sigma modulator

Techniques for determining a fault probability of a location on a chip

Bit sequence generator and apparatus for calculating a sub-rate transition matrix and a sub-rate initial state for a state machine of a plurality of state machines

Method and apparatus for adjusting transitions in a bit stream

Apparatus for determining a number of successive equal bits preceding an edge within a bit stream and apparatus for reconstructing a repetitive bit sequence

State machine and generator for generating a description of a state machine feedback function

AGILENT TECHNOLOGIES INC

Method and apparatus for testing digital devices using transition timestamps

Sigma-delta modulator with PWM output

Analog to digital signal conversion method and apparatus

Analog to digital conversion method using track/hold circuit and time interval analyzer, and an apparatus using the method

Signal preconditioning for analog-to-digital conversion with timestamps

Test vector compression method

Method and apparatus for analog to digital conversion using time-varying reference signal

Analog signal test using a-priori information

Using component-level calibration data to reduce system-level test

Precision pulse placement to form a binary pulse signal

Unidirectional verification of bus-based systems

Digital signal transition splitting method and apparatus

VERIGY PTE LTD SINGAPORE

Re-configurable architecture for automated test equipment

Time-to-digital conversion with calibration pulse injection

Method and system for per-pin clock synthesis of an electronic device under test

Digital to analog conversion using summation of multiple DACs

Parameterized signal conditioning

Time-to-digital conversion with delay contribution determination of delay elements

Asynchronous sigma-delta digital-analog converter

Fast synchronization of a number of digital clocks

Transition tracking

Method and system for digital to analog conversion using multi-purpose current summation

ADVANTEST CORP

Systems and methods for device testing to avoid resource conflicts for a large number of test scenarios

Tester and method for testing a device under test using relevance scores

Tester and method for testing a device under test and tester and method for determining a single decision function

Automated test equipment for combined signals

Test apparatus for performing a test on a device under test and data set filter for filtering a data set to obtain a best setting of a device under test

Test apparatus and method for characterizing a device under test

Test apparatus and method for testing a device under test

HEWLETT PACKARD CO

Event recognition by a state machine whose state is dependent upon historical information

Test permutator

ADVANTEST SINGAPORE PTE LTD

Device under test data processing techniques

Evaluation of an output signal of a device under test

VERIGG IPCO

Bandwidth matching for scan architectures in an integrated circuit

PAUSINI MARCO

Apparatus comprising a recursive delayer and method for measuring a phase noise