Inventor

WIECZOREK KARSTEN

DE79 patents

Patents

50 patents

US6274894B1Aug 14, 2001

Low-bandgap source and drain formation for short-channel MOS transistors

ADVANCED MICRO DEVICES INC205 citations99

US7297994B2Nov 20, 2007

Semiconductor device having a retrograde dopant profile in a channel region

ADVANCED MICRO DEVICES INC117 citations98

US6881641B2Apr 19, 2005

Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same

ADVANCED MICRO DEVICES INC132 citations98

US6838363B2Jan 4, 2005

Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material

ADVANCED MICRO DEVICES INC54 citations96

US6255703B1Jul 3, 2001

Device with lower LDD resistance

ADVANCED MICRO DEVICES INC69 citations96

US6352885B1Mar 5, 2002

Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same

ADVANCED MICRO DEVICES INC46 citations93

US6274511B1Aug 14, 2001

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer

ADVANCED MICRO DEVICES INC25 citations93

US6255214B1Jul 3, 2001

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions

ADVANCED MICRO DEVICES INC38 citations93

US6242776B1Jun 5, 2001

Device improvement by lowering LDD resistance with new silicide process

ADVANCED MICRO DEVICES INC41 citations93

US6218250B1Apr 17, 2001

Method and apparatus for minimizing parasitic resistance of semiconductor devices

ADVANCED MICRO DEVICES INC19 citations93

US6165903ADec 26, 2000

Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation

ADVANCED MICRO DEVICES INC29 citations93

US6150243ANov 21, 2000

Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer

ADVANCED MICRO DEVICES INC46 citations93

US6133124AOct 17, 2000

Device improvement by source to drain resistance lowering through undersilicidation

ADVANCED MICRO DEVICES INC38 citations93

US6121138ASep 19, 2000

Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging

ADVANCED MICRO DEVICES INC20 citations93

US7060549B1Jun 13, 2006

SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same

ADVANCED MICRO DEVICES INC36 citations92

US6812115B2Nov 2, 2004

Method of filling an opening in a material layer with an insulating material

ADVANCED MICRO DEVICES INC26 citations92

US6723663B1Apr 20, 2004

Technique for forming an oxide/nitride layer stack by controlling the nitrogen ion concentration in a nitridation plasma

ADVANCED MICRO DEVICES INC26 citations92

US6620718B1Sep 16, 2003

Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device

ADVANCED MICRO DEVICES INC47 citations92

US6566718B2May 20, 2003

Field effect transistor with an improved gate contact and method of fabricating the same

ADVANCED MICRO DEVICES INC33 citations92

US6541863B1Apr 1, 2003

Semiconductor device having a reduced signal processing time and a method of fabricating the same

ADVANCED MICRO DEVICES INC20 citations92

US6423634B1Jul 23, 2002

Method of forming low resistance metal silicide region on a gate electrode of a transistor

ADVANCED MICRO DEVICES INC27 citations92

US6306698B1Oct 23, 2001

Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same

ADVANCED MICRO DEVICES INC46 citations92

US6271122B1Aug 7, 2001

Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices

ADVANCED MICRO DEVICES INC37 citations92

US6268257B1Jul 31, 2001

Formation of junctions by diffusion from a doped film into and through a silicide during silicidation

ADVANCED MICRO DEVICES INC27 citations92

US6344397B1Feb 5, 2002

Semiconductor device having a gate electrode with enhanced electrical characteristics

ADVANCED MICRO DEVICES INC24 citations90

US6383906B1May 7, 2002

Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption

ADVANCED MICRO DEVICES INC29 citations89

US7955937B2Jun 7, 2011

Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors

ADVANCED MICRO DEVICES INC7 citations84

US7238578B2Jul 3, 2007

Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions

ADVANCED MICRO DEVICES INC15 citations84

US7217657B2May 15, 2007

Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device

ADVANCED MICRO DEVICES INC13 citations84

US7192881B2Mar 20, 2007

Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity

ADVANCED MICRO DEVICES INC14 citations84

US7122410B2Oct 17, 2006

Polysilicon line having a metal silicide region enabling linewidth scaling including forming a second metal silicide region on the substrate

ADVANCED MICRO DEVICES INC15 citations84

US6821887B2Nov 23, 2004

Method of forming a metal silicide gate in a standard MOS process sequence

ADVANCED MICRO DEVICES INC18 citations84

US6821840B2Nov 23, 2004

Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area

ADVANCED MICRO DEVICES INC13 citations84

US6746927B2Jun 8, 2004

Semiconductor device having a polysilicon line structure with increased metal silicide portions and method for forming the polysilicon line structure of a semiconductor device

ADVANCED MICRO DEVICES INC15 citations84

US6593197B2Jul 15, 2003

Sidewall spacer based fet alignment technology

ADVANCED MICRO DEVICES INC16 citations84

US6207563B1Mar 27, 2001

Low-leakage CoSi2-processing by high temperature thermal processing

ADVANCED MICRO DEVICES INC16 citations84

US6169005B1Jan 2, 2001

Formation of junctions by diffusion from a doped amorphous silicon film during silicidation

ADVANCED MICRO DEVICES INC16 citations84

US6281086B1Aug 28, 2001

Semiconductor device having a low resistance gate conductor and method of fabrication the same

ADVANCED MICRO DEVICES INC17 citations80

US6849516B2Feb 1, 2005

Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer

ADVANCED MICRO DEVICES INC11 citations74

US6812074B2Nov 2, 2004

SOI field effect transistor element having a recombination region and method of forming same

ADVANCED MICRO DEVICES INC11 citations74

US6806126B1Oct 19, 2004

Method of manufacturing a semiconductor component

ADVANCED MICRO DEVICES INC12 citations74

US6798028B2Sep 28, 2004

Field effect transistor with reduced gate delay and method of fabricating the same

ADVANCED MICRO DEVICES INC12 citations74

US6754553B2Jun 22, 2004

Implant monitoring using multiple implanting and annealing steps

ADVANCED MICRO DEVICES INC9 citations74

US6673665B2Jan 6, 2004

Semiconductor device having increased metal silicide portions and method of forming the semiconductor

ADVANCED MICRO DEVICES INC10 citations74

US6555892B2Apr 29, 2003

Semiconductor device with reduced line-to-line capacitance and cross talk noise

ADVANCED MICRO DEVICES INC12 citations74

US6410410B1Jun 25, 2002

Method of forming lightly doped regions in a semiconductor device

ADVANCED MICRO DEVICES INC8 citations74

Showing the top 50 of 79 patents by PatentIndex Score.

WIECZOREK KARSTEN

Patents

Low-bandgap source and drain formation for short-channel MOS transistors

Semiconductor device having a retrograde dopant profile in a channel region

Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same

Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material

Device with lower LDD resistance

Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer

Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions

Device improvement by lowering LDD resistance with new silicide process

Method and apparatus for minimizing parasitic resistance of semiconductor devices

Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation

Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer

Device improvement by source to drain resistance lowering through undersilicidation

Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging

SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same

Method of filling an opening in a material layer with an insulating material

Technique for forming an oxide/nitride layer stack by controlling the nitrogen ion concentration in a nitridation plasma

Method of forming metal silicide regions on a gate electrode and on the source/drain regions of a semiconductor device

Field effect transistor with an improved gate contact and method of fabricating the same

Semiconductor device having a reduced signal processing time and a method of fabricating the same

Method of forming low resistance metal silicide region on a gate electrode of a transistor

Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same

Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices

Method of forming a transistor having a low-resistance gate electrode

Formation of junctions by diffusion from a doped film at silicidation

Multi-depth junction formation tailored to silicide formation

Silicidation with silicon buffer layer and silicon spacers

Formation of junctions by diffusion from a doped film into and through a silicide during silicidation

Semiconductor device having a gate electrode with enhanced electrical characteristics

Method of forming junction-leakage free metal salicide in a semiconductor wafer with ultra-low silicon consumption

Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors

Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions

Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device

Method of forming sidewall spacer elements for a circuit element by increasing an etch selectivity

Polysilicon line having a metal silicide region enabling linewidth scaling including forming a second metal silicide region on the substrate

Method of forming a metal silicide gate in a standard MOS process sequence

Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area

Semiconductor device having a polysilicon line structure with increased metal silicide portions and method for forming the polysilicon line structure of a semiconductor device

Sidewall spacer based fet alignment technology

Low-leakage CoSi2-processing by high temperature thermal processing

Formation of junctions by diffusion from a doped amorphous silicon film during silicidation

Semiconductor device having a low resistance gate conductor and method of fabrication the same

Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer

SOI field effect transistor element having a recombination region and method of forming same

Method of manufacturing a semiconductor component

Field effect transistor with reduced gate delay and method of fabricating the same

Implant monitoring using multiple implanting and annealing steps

Semiconductor device having increased metal silicide portions and method of forming the semiconductor

Semiconductor device with reduced line-to-line capacitance and cross talk noise

Method of forming lightly doped regions in a semiconductor device