Inventor

HORSTMANN MANFRED

DE84 patents

⚠️ This page may combine multiple inventors who share the name “HORSTMANN MANFRED”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HORSTMANN MANFRED

ADVANCED MICRO DEVICES INC

Low-bandgap source and drain formation for short-channel MOS transistors

Semiconductor device having a retrograde dopant profile in a channel region

Semiconductor device having a retrograde dopant profile in a channel region and method for fabricating the same

Circuit element having a metal silicide region thermally stabilized by a barrier diffusion material

Device with lower LDD resistance

Self-biasing transistor structure and an SRAM cell having less than six transistors

Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same

Embedded strain layer in thin SOI transistors and a method of forming the same

Technique for providing multiple stress sources in NMOS and PMOS transistors

Transistor having a peripherally increased gate insulation thickness and a method of fabricating the same

Device improvement by lowering LDD resistance with new silicide process

Method and apparatus for minimizing parasitic resistance of semiconductor devices

Device improvement by source to drain resistance lowering through undersilicidation

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same

SRAM devices utilizing tensile-stressed strain films and methods for fabricating the same

Field effect transistor with an improved gate contact and method of fabricating the same

Semiconductor device having a reduced signal processing time and a method of fabricating the same

Semiconductor device having a gate electrode with enhanced electrical characteristics

Method for manufacturing semiconductor device comprising SOI transistors and bulk transistors

Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device

SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions

Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device

Technique for forming contacts for buried doped regions in a semiconductor device

Semiconductor device having improved doping profiles and a method of improving the doping profiles of a semiconductor device

Method of forming a metal silicide gate in a standard MOS process sequence

Sidewall spacer based fet alignment technology

Method of controlling a shape of an oxide layer formed on a substrate

Low-leakage CoSi2-processing by high temperature thermal processing

SOI transistor having a reduced body potential and a method of forming the same

Method of making a semiconductor device comprising isolation trenches inducing different types of strain

Semiconductor device having a low resistance gate conductor and method of fabrication the same

Transistor device having an increased threshold stability without drive current degradation

Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer

SOI field effect transistor element having a recombination region and method of forming same

Field effect transistor with reduced gate delay and method of fabricating the same

Implant monitoring using multiple implanting and annealing steps

Semiconductor device having increased metal silicide portions and method of forming the semiconductor

Semiconductor device with reduced line-to-line capacitance and cross talk noise

Method of forming lightly doped regions in a semiconductor device

Device improvement by lowering LDD resistance with new spacer/silicide process

Method of forming a gate structure of a transistor by means of scalable spacer technology

Tensile strain source using silicon/germanium in globally strained silicon

Field effect transistor comprising a stressed channel region and method of forming the same

Technique for providing stress sources in MOS transistors in close proximity to a channel region

CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure

GLOBALFOUNDRIES INC

Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same

Method of forming a semiconductor structure