Inventor

ROBERTS CEREDIG

US36 patents

⚠️ This page may combine multiple inventors who share the name “ROBERTS CEREDIG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROBERTS CEREDIG

MICRON TECHNOLOGY INC

Method of forming high aspect ratio structures for semiconductor devices

BiCMOS process and process for forming bipolar transistors on wafers also containing FETs

Dual-masked isolation

Dual-masked field isolation

Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer

Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer

Oxide etching method and structures resulting from same

Method of making straight wall containers and the resultant containers

Dual-masked field isolation

Facet etch for improved step coverage of integrated circuit contacts

Facet etch for improved step coverage of integrated circuit contacts

Method of manufacturing a memory device

Method for patterning cavities and enhanced cavity shapes for semiconductor devices

SRAM cell employing substantially vertically elongated pull-up resistors

Method for forming MOS transistors

Oxide etching method and structures resulting from same

Raised-lines overlay semiconductor targets and method of making the same

Facet etch for improved step coverage of integrated circuit contacts

SRAM cell employing substantially vertically elongated pull-up resistors

Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxide MOSFETs

Method of forming transistors in a peripheral circuit of a semiconductor memory device

Semiconductor memory device and method of forming transistors in a peripheral circuit of the semiconductor memory device

SCRAM cell employing substantially vertically elongated pull-up resistors

SRAM cell employing substantially vertically elongated pull-up resistors

SRAM cell employing substantially vertically elongated pull-up resistors

Residue free overlay target

Memory device

Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs

Method of making straight wall containers and the resultant containers

Method of forming transistors in a peripheral circuit of a semiconductor memory device

SRAM cell employing substantially vertically elongated pull-up resistors

SRAM cell employing substantially vertically elongated pull-up resistors

SRAM cell employing substantially vertically elongated pull-up resistors

Capacitor structure for two-transistor DRAM memory cell and method of forming same

Sram cell employing substantially vertically elongated pull-up resistors

PAREKH KUNAL

Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline