P

Inventor

LU AIGUO

US22 patents
⚠️ This page may combine multiple inventors who share the name “LU AIGUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI LOGIC CORP

17 patents
US6550044B1Apr 15, 2003

Method in integrating clock tree synthesis and timing optimization for an integrated circuit design

LSI LOGIC CORP59 citations96
US6550045B1Apr 15, 2003

Changing clock delays in an integrated circuit for skew optimization

LSI LOGIC CORP88 citations95
US7096442B2Aug 22, 2006

Optimizing IC clock structures by minimizing clock uncertainty

LSI LOGIC CORP18 citations92
US6637016B1Oct 21, 2003

Assignment of cell coordinates

LSI LOGIC CORP27 citations92
US6546541B1Apr 8, 2003

Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances

LSI LOGIC CORP52 citations92
US6487697B1Nov 26, 2002

Distribution dependent clustering in buffer insertion of high fanout nets

LSI LOGIC CORP24 citations92
US6629304B1Sep 30, 2003

Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells

LSI LOGIC CORP16 citations84
US6557144B1Apr 29, 2003

Netlist resynthesis program based on physical delay calculation

LSI LOGIC CORP16 citations84
US7356785B2Apr 8, 2008

Optimizing IC clock structures by minimizing clock uncertainty

LSI LOGIC CORP11 citations83
US6810515B2Oct 26, 2004

Process of restructuring logics in ICs for setup and hold time optimization

LSI LOGIC CORP12 citations74
US6701493B2Mar 2, 2004

Floor plan tester for integrated circuit design

LSI LOGIC CORP12 citations74
US6470487B1Oct 22, 2002

Parallelization of resynthesis

LSI LOGIC CORP10 citations74
US6934733B1Aug 23, 2005

Optimization of adder based circuit architecture

LSI LOGIC CORP8 citations71
US6691283B1Feb 10, 2004

Optimization of comparator architecture

LSI LOGIC CORP7 citations71
US6553551B1Apr 22, 2003

Timing recomputation

LSI LOGIC CORP2 citations63
US6463572B1Oct 8, 2002

IC timing analysis with known false paths

LSI LOGIC CORP5 citations63
US6868536B2Mar 15, 2005

Method to find boolean function symmetries

LSI LOGIC CORP6 citations62

NIKITIN ANDREY

2 patents

LSI CORP

2 patents

SYNOPSYS INC

1 patent