Inventor
ZOLOTYKH ANDREJ A
RU24 patents
⚠️ This page may combine multiple inventors who share the name “ZOLOTYKH ANDREJ A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
18 patentsUS6550044B1Apr 15, 2003
Method in integrating clock tree synthesis and timing optimization for an integrated circuit design
LSI LOGIC CORP59 citations96
US6681373B1Jan 20, 2004
Method and apparatus for dynamic buffer and inverter tree optimization
LSI LOGIC CORP22 citations92
US6637016B1Oct 21, 2003
Assignment of cell coordinates
LSI LOGIC CORP27 citations92
US6564361B1May 13, 2003
Method and apparatus for timing driven resynthesis
LSI LOGIC CORP44 citations92
US6543032B1Apr 1, 2003
Method and apparatus for local resynthesis of logic trees with multiple cost functions
LSI LOGIC CORP33 citations92
US6487697B1Nov 26, 2002
Distribution dependent clustering in buffer insertion of high fanout nets
LSI LOGIC CORP24 citations92
US6629304B1Sep 30, 2003
Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells
LSI LOGIC CORP16 citations84
US6651239B1Nov 18, 2003
Direct transformation of engineering change orders to synthesized IC chip designs
LSI LOGIC CORP16 citations83
US6637011B1Oct 21, 2003
Method and apparatus for quick search for identities applicable to specified formula
LSI LOGIC CORP13 citations83
US6532582B1Mar 11, 2003
Method and apparatus for optimal critical netlist area selection
LSI LOGIC CORP17 citations83
US6810515B2Oct 26, 2004
Process of restructuring logics in ICs for setup and hold time optimization
LSI LOGIC CORP12 citations74
US6701493B2Mar 2, 2004
Floor plan tester for integrated circuit design
LSI LOGIC CORP12 citations74
US6470487B1Oct 22, 2002
Parallelization of resynthesis
LSI LOGIC CORP10 citations74
US6553551B1Apr 22, 2003
Timing recomputation
LSI LOGIC CORP2 citations63
US6868536B2Mar 15, 2005
Method to find boolean function symmetries
LSI LOGIC CORP6 citations62
US6701503B2Mar 2, 2004
Overlap remover manager
LSI LOGIC CORP1 citations52
US7146591B2Dec 5, 2006
Method of selecting cells in logic restructuring
LSI LOGIC CORP1 citations50
US7111267B2Sep 19, 2006
Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths
LSI LOGIC CORP0 citations50
LSI CORP
5 patentsUS7398486B2Jul 8, 2008
Method and apparatus for performing logical transformations for global routing
LSI CORP4 citations62
US7496870B2Feb 24, 2009
Method of selecting cells in logic restructuring
LSI CORP3 citations61
US7257791B2Aug 14, 2007
Multiple buffer insertion in global routing
LSI CORP3 citations61
US7568175B2Jul 28, 2009
Ramptime propagation on designs with cycles
LSI CORP0 citations48
US7246336B2Jul 17, 2007
Ramptime propagation on designs with cycles
LSI CORP0 citations48