Inventor

GASANOV ELYAR E

RU51 patents

⚠️ This page may combine multiple inventors who share the name “GASANOV ELYAR E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GASANOV ELYAR E

LSI LOGIC CORP

Method and apparatus for parallel simultaneous global and detail routing

Net routing using basis element decomposition

Method and apparatus for hierarchical global routing descend

Method in integrating clock tree synthesis and timing optimization for an integrated circuit design

Changing clock delays in an integrated circuit for skew optimization

Method and apparatus for dynamic buffer and inverter tree optimization

Assignment of cell coordinates

Method and apparatus for timing driven resynthesis

Method and apparatus for local resynthesis of logic trees with multiple cost functions

Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells

Method and apparatus for quick search for identities applicable to specified formula

Method and apparatus for optimal critical netlist area selection

Multidirectional router

Process of restructuring logics in ICs for setup and hold time optimization

Floor plan tester for integrated circuit design

Parallelization of resynthesis

Blocked net buffer insertion

Timing recomputation

Process and apparatus for placement of megacells in ICs design

Method and apparatus for finding optimal unification substitution for formulas in technology library

Method to find boolean function symmetries

Overlap remover manager

Density driven assignment of coordinates

Method of selecting cells in logic restructuring

Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths

LSI CORP

Systems and methods for area efficient data encoding

Method and apparatus for performing logical transformations for global routing

Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder

Method of selecting cells in logic restructuring

Multiple buffer insertion in global routing

Method and apparatus for controlling congestion during integrated circuit design resynthesis

Ramptime propagation on designs with cycles

Ramptime propagation on designs with cycles

PANTELEEV PAVEL A

Scheme for erasure locator polynomial calculation in error-and-erasure decoder

Variable parity encoder

Reconfigurable encoding per multiple communications standards

Branch metrics calculation for multiple communications standards

Reconfigurable BCH decoder

SOKOLOV ANDREY P

Parallel decoder for multiple wireless standards

Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards

L-value generation in a decoder

SHUTKIN YURII S

Two-pass linear complexity task scheduler

No-delay microsequencer

GASANOV ELYAR E

Timer manager architecture based on binary heap

Radix-4 viterbi forward error correction decoding

NEZNANOV ILYA V

BCH or reed-solomon decoder with syndrome modification

ANDREEV ALEXANDER

Configurable Reed-Solomon decoder based on modified Forney syndromes

ANDREEV ALEXANDER E

System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors

LSICorporation

Low area architecture in BCH decoder

ALISEYCHIK PAVEL A

Parallel true random number generator architecture