Inventor

ANVIN H PETER

US56 patents

⚠️ This page may combine multiple inventors who share the name “ANVIN H PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANVIN H PETER

TRANSMETA CORP

System and method for identifying TLB entries associated with a physical address of a specified range

System and method for identifying TLB entries associated with a physical address of a specified range

Adaptive power control

System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored

Translation consistency checking for modified target instructions by comparing to original copy

Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation

Fine grain translation discrimination

Use of MTRR and page attribute table to support multiple byte order formats in a computer system

Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold

Method and system for caching attribute data for matching attributes with physical addresses

Method and system for caching attribute data for matching attributes with physical addresses

Method of determining a mode of code generation

Method of changing modes of code generation

Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions

Explicit control of speculation

Method and system for implementing a floating point compare using recorded flags

Method and apparatus for handling nested faults

Method and apparatus for improving segmented memory addressing

Method and apparatus for improving segmented memory addressing

INTEL CORP

Handling of binary translated self modifying code and cross modifying code

Instructions and logic to provide memory access key protection functionality

Methods, apparatus, and instructions for user-level thread suspension

Protecting supervisor mode information

Shadow stack ISA extensions to support fast return and event delivery (FRED) architecture

Shadow stack ISA extensions to support fast return and event delivery (FRED) architecture

Methods, apparatus, and instructions for user level thread suspension

Protecting supervisor mode information

Protecting supervisor mode information

System, apparatus and methods for performant read and write of processor state information responsive to list instructions

ANVIN H PETER

Method and apparatus for handling nested faults

Method and system for caching attribute data for matching attributes with physical addresses

Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

Supporting multiple byte order formats in a computer system

Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

Method and system for caching attribute data for matching attributes with physical addresses

INTELLECTUAL VENTURE FUNDING LLC

Method and system for caching attribute data for matching attributes with physical addresses

Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

Adaptive power control

ROZAS GUILLERMO

System and method for identifying TLB entries associated with a physical address of a specified range

System and method for identifying TLB entries associated with a physical address of a specified range

JOHNSON RICHARD C

Architecture, system, and method for operating on encrypted and/or hidden information

Architecture, system, and method for operating on encrypted and/or hidden information

HALEPETE SAMEER

Adaptive power control

Adaptive power control

FLEISCHMANN MARC

System and method for saving and restoring a processor state without executing any instructions from a first instruction set

Restoring processor context in response to processor power-up

BANNING JOHN

Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur

Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version

MORGAN ANDREW

System with secure cryptographic capabilities using a hardware specific digital secret