Inventor

RENTSCHLER ERIC M

US23 patents

⚠️ This page may combine multiple inventors who share the name “RENTSCHLER ERIC M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RENTSCHLER ERIC M

HEWLETT PACKARD DEVELOPMENT CO

Memory controller with 1X/MX write capability

Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices

Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data

Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad

Synchronizing link delay measurement over serial links

Memory controller receiver circuitry with tri-state noise immunity

Memory controller to communicate with memory devices that are associated with differing data/strobe ratios

Mirrored computer memory on split bus

Repeatability over communication links

HEWLETT PACKARD CO

Caching and coherency control of multiple geometry accelerators in a computer graphics system

Computer graphics system utilizing parallel processing for enhanced performance

Coherency protocol for computer cache

Circuit for finding m modulo n

Mechanism for implementing bus locking with a mixed architecture

Data bus protocol for computer graphics system

NIXON SCOTT P

Distributed on-chip debug triggering with allocated bus lines

Multiple clock domain tracing

Multiple clock domain debug capability

Method and apparatus for on-chip debugging

RENTSCHLER ERIC M

Debug state machines and methods of their operation

Debug state machine cross triggering

(unassigned)

Memory controller with 1×/M× read capability

BEDWELL RYAN D

Correlating traces in a computing system