Inventor
PEREZ MICHAEL ANTHONY
US16 patents
Patents
16 patentsUS6658599B1Dec 2, 2003
Method for recovering from a machine check interrupt during runtime
IBM60 citations93
US7107495B2Sep 12, 2006
Method, system, and product for improving isolation of input/output errors in logically partitioned data processing systems
IBM21 citations92
US7103808B2Sep 5, 2006
Apparatus for reporting and isolating errors below a host bridge
IBM24 citations92
US6662318B1Dec 9, 2003
Timely error data acquistion
IBM33 citations87
US6473814B1Oct 29, 2002
System for optimally tuning a burst length by setting a maximum burst length based on a latency timer value and adjusting the maximum burst length based on a cache line size
IBM31 citations87
US6976191B2Dec 13, 2005
Method and apparatus for analyzing hardware errors in a logical partitioned data processing system
IBM13 citations83
US6898686B1May 24, 2005
Memory map adjustment to support the need of adapters with large memory requirements
IBM14 citations83
US7146515B2Dec 5, 2006
System and method for selectively executing a reboot request after a reset to power on state for a particular partition in a logically partitioned system
IBM14 citations82
US6704823B1Mar 9, 2004
Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing
IBM17 citations82
US6820161B1Nov 16, 2004
Mechanism for allowing PCI-PCI bridges to cache data without any coherency side effects
IBM11 citations73
US6665753B1Dec 16, 2003
Performance enhancement implementation through buffer management/bridge settings
IBM12 citations73
US6834363B2Dec 21, 2004
Method for prioritizing bus errors
IBM11 citations72
US6898644B1May 24, 2005
Method of programming I/O adapter settings for optimal performance
IBM2 citations62
US6697940B1Feb 24, 2004
Mechanism to disable the gathering of time consuming unnecessary information at boottime
IBM6 citations60
US6519555B1Feb 11, 2003
Apparatus and method of allowing PCI v1.0 devices to work in PCI v2.0 compliant system
IBM3 citations59
US6662320B1Dec 9, 2003
Method and apparatus for inhibiting an adapter bus error signal following a reset operation
IBM1 citations51