Inventor

MICHAEL MARK W

US105 patents

⚠️ This page may combine multiple inventors who share the name “MICHAEL MARK W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MICHAEL MARK W

ADVANCED MICRO DEVICES INC

Method and apparatus for in situ anneal during ion implant

Dissolvable dielectric method

Substantially planar semiconductor topography using dielectrics and chemical mechanical polish

Method of formation of an air gap within a semiconductor dielectric by solvent desorption

Method of making NMOS and PMOS devices with reduced masking steps

Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths

Transistor with buried insulative layer beneath the channel region

Method of channel doping using diffusion from implanted polysilicon

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines

Interlevel dielectric with air gaps to reduce permitivity

Multiple split gate semiconductor device and fabrication method

Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion

Interlevel dielectric with air gaps to lessen capacitive coupling

Trench transistor with insulative spacers

Method of making an IGFET with a multilevel gate

Method for achieving global planarization by forming minimum mesas in large field areas

Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device

Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

Reticle that compensates for radiation-induced lens error in a photolithographic system

Individually controllable radiation sources for providing an image pattern in a photolithographic system

Interlevel dielectric with air gaps to lessen capacitive coupling

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

Method of forming a shallow junction by diffusion from a silicon-based spacer

Method to reduce parasitic capacitance of MOS transistors

Tri-level segmented control transistor and fabrication method

Photolithographic system including light filter that compensates for lens error

Dopant diffusion-retarding barrier region formed within polysilicon gate layer

Dielectric having an air gap formed between closely spaced interconnect lines

Method for forming integrated circuit gate conductors from dual layers of polysilicon

Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls

Method of forming an insulated-gate field-effect transistor with metal spacers

System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication

Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance

Method of forming trench transistor with insulative spacers

Dissolvable dielectric method and structure

Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls

Ion implantation into a gate electrode layer using an implant profile displacement layer

Method and structure for isolating semiconductor devices after transistor formation

Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching

Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device

Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device

Method of planarizing a semiconductor topography using multiple polish pads

Trench transistor with metal spacers

Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls

Method of making an integrated circuit with oxidizable trench liner

Integrated circuit having local interconnect for reducing signal cross coupled noise

Method of making an igfet with selectively doped multilevel polysilicon gate

Method of reducing overlap between gate electrode and LDD region

ADVANCED MICRO DEVCIES INC

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect