Inventor
GATES STEPHEN MCCONNELL
US43 patents
⚠️ This page may combine multiple inventors who share the name “GATES STEPHEN MCCONNELL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
41 patentsUS6479110B2Nov 12, 2002
Multiphase low dielectric constant material and method of deposition
IBM175 citations99
US6437443B1Aug 20, 2002
Multiphase low dielectric constant material and method of deposition
IBM152 citations99
US6312793B1Nov 6, 2001
Multiphase low dielectric constant material
IBM320 citations99
US6271542B1Aug 7, 2001
Merged logic and memory combining thin film and bulk Si transistors
IBM119 citations99
US6203613B1Mar 20, 2001
Atomic layer deposition with nitrate containing precursors
IBM1,649 citations99
US5796121AAug 18, 1998
Thin film transistors fabricated on plastic substrates
IBM161 citations99
US7491658B2Feb 17, 2009
Ultra low k plasma enhanced chemical vapor deposition processes using a single bifunctional precursor containing both a SiCOH matrix functionality and organic porogen functionality
IBM63 citations98
US6737727B2May 18, 2004
Electronic structures with reduced capacitance
IBM44 citations96
US6677680B2Jan 13, 2004
Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials
IBM54 citations96
US6620659B2Sep 16, 2003
Merged logic and memory combining thin film and bulk Si transistors
IBM349 citations96
US6603204B2Aug 5, 2003
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
IBM54 citations96
US6285050B1Sep 4, 2001
Decoupling capacitor structure distributed above an integrated circuit and method for making same
IBM71 citations96
US6180444B1Jan 30, 2001
Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same
IBM69 citations96
US5799231AAug 25, 1998
Variable index distributed mirror
IBM81 citations96
US7371461B2May 13, 2008
Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics
IBM13 citations93
US7288292B2Oct 30, 2007
Ultra low k (ULK) SiCOH film and method
IBM49 citations93
US6958526B2Oct 25, 2005
Electronic structures with reduced capacitance
IBM17 citations93
US6780499B2Aug 24, 2004
Ordered two-phase dielectric film, and semiconductor device containing the same
IBM24 citations93
US6756324B1Jun 29, 2004
Low temperature processes for making electronic device structures
IBM39 citations93
US6351023B1Feb 26, 2002
Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same
IBM28 citations93
US5830538ANov 3, 1998
Method to form a polycrystalline film on a substrate
IBM67 citations93
US6943451B2Sep 13, 2005
Semiconductor devices containing a discontinuous cap layer and methods for forming same
IBM21 citations92
US6831366B2Dec 14, 2004
Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer
IBM19 citations92
US6737107B2May 18, 2004
Nonoparticles formed with rigid connector compounds
IBM16 citations92
US6716742B2Apr 6, 2004
Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
IBM24 citations92
US6599623B2Jul 29, 2003
Nanoparticles formed with rigid connector compounds
IBM18 citations92
US6562634B2May 13, 2003
Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same
IBM26 citations92
US6548901B1Apr 15, 2003
Cu/low-k BEOL with nonconcurrent hybrid dielectric interface
IBM22 citations92
US6440560B1Aug 27, 2002
Nanoparticles formed with rigid connector compounds
IBM26 citations92
US6784485B1Aug 31, 2004
Diffusion barrier layer and semiconductor device containing same
IBM25 citations91
US5667586ASep 16, 1997
Method for forming a single crystal semiconductor on a substrate
IBM78 citations90
US7357977B2Apr 15, 2008
Ultralow dielectric constant layer with controlled biaxial stress
IBM10 citations83
US6537908B2Mar 25, 2003
Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask
IBM16 citations82
US7811926B2Oct 12, 2010
Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics
IBM6 citations74
US7256146B2Aug 14, 2007
Method of forming a ceramic diffusion barrier layer
IBM5 citations74
US6940173B2Sep 6, 2005
Interconnect structures incorporating low-k dielectric barrier films
IBM6 citations74
US6724069B2Apr 20, 2004
Spin-on cap layer, and semiconductor device containing same
IBM12 citations73
US6710450B2Mar 23, 2004
Interconnect structure with precise conductor resistance and method to form same
IBM11 citations73
US6657305B1Dec 2, 2003
Semiconductor recessed mask interconnect technology
IBM12 citations72
US6726996B2Apr 27, 2004
Laminated diffusion barrier
IBM8 citations69
US7252875B2Aug 7, 2007
Diffusion barrier with low dielectric constant and semiconductor device containing same
IBM2 citations63