Inventor

NITTA SATYANARAYANA V

US78 patents

⚠️ This page may combine multiple inventors who share the name “NITTA SATYANARAYANA V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NITTA SATYANARAYANA V

IBM

Method for forming a porous dielectric material layer in a semiconductor device and device formed

Interconnect structures with fully aligned vias

Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby

Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby

Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same

Device and methodology for reducing effective dielectric constant in semiconductor devices

Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics

Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials

Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same

Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics

Device and methodology for reducing effective dielectric constant in semiconductor devices

Multilayer interconnect structure containing air gaps and method for making

Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence

Ordered two-phase dielectric film, and semiconductor device containing the same

Semiconductor devices containing a discontinuous cap layer and methods for forming same

Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer

Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics

Fine-pitch device lithography using a sacrificial hardmask

Interconnect structures with fully aligned vias

Methods for fabrication of an air gap-containing interconnect structure

Method for fabricating air gap interconnect structures

Device and methodology for reducing effective dielectric constant in semiconductor devices

Sub-lithographic dimensioned air gap formation and related structure

Embedded nano UV blocking and diffusion barrier for improved reliability of copper/ultra low K interlevel dielectric electronic devices

Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics

Method of producing self-aligned mask in conjunction with blocking mask, articles produced by same and composition for same

Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity

Providing targeted, evidence-based recommendations to improve content by combining static analysis and usage analysis

Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask

Air gap structure having protective metal silicide pads on a metal feature

Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same

Device and methodology for reducing effective dielectric constant in semiconductor devices

Method for forming a porous dielectric material layer in a semiconductor device and device formed

Recommending personalized job recommendations from automated review of writing samples and resumes

Interconnect structures with fully aligned vias

Spin-on cap layer, and semiconductor device containing same

Interconnect structure with precise conductor resistance and method to form same

EDELSTEIN DANIEL C

Reliable physical unclonable function for device authentication

Microelectronic structure including air gap

Reducing effective dielectric constant in semiconductor devices

Microelectronic structure including air gap

CLEVENGER LAWRENCE A

Method for air gap interconnect integration using photo-patternable low k material

Methods for fabrication of an air gap-containing interconnect structure

CHANDA KAUSHIK

Air gap interconnect structures and methods for forming the same

BRUCE ROBERT L

Interconnect structure and method for fabricating on-chip interconnect structures by image reversal

NGUYEN SON VAN

Interlevel dielectric stack for interconnect structures

GATES STEPHEN M

BEOL structures incorporating active devices and mechanical strength

CABRAL JR CYRIL

Interconnect structure for improved time dependent dielectric breakdown

ANGYAL MATTHEW S

Deep trench crackstops under contacts

GLOBALFOUNDRIES INC

BEOL structures incorporating active devices and mechanical strength