Inventor

KIM SARAH E

US44 patents

⚠️ This page may combine multiple inventors who share the name “KIM SARAH E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM SARAH E

INTEL CORP

Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack

Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration

Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof

Etch thinning techniques for wafer-to-wafer vertical stacks

Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same

Thinning techniques for wafer-to-wafer vertical stacks

Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack

Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack

3D integrated circuits using thick metal for backside connections and offset bumps

Methods of forming backside connections on a wafer stack

Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow

Methods of forming backside connections on a wafer stack

Ultra-high capacitance device based on nanostructures

Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack

Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack

Thick metal layer integrated process flow to improve power delivery and mechanical buffering

Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips

Method and apparatus for low temperature copper to copper bonding

Self-aligned electrodes contained within the trenches of an electroosmotic pump

Capacitor with conducting nanostructure

Cooling micro-channels

Using external radiators with electroosmotic pumps for cooling integrated circuits

Method and structure for interfacing electronic devices

Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode

Electro-osmotic pumps and micro-channels

Ultra-high capacitance device based on nanostructures

Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same

Three-dimensional stacked substrate arrangements

Cooling micro-channels

Capacitor with insulating nanostructure

Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode

Electroosmotic pumps using porous frits for cooling integrated circuit stacks

Differential planarization

Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same

Packaged electroosmotic pumps using porous frits for cooling integrated circuits

Fabrication of 3-D capacitor with dual damascene process

Method and structure for interfacing electronic devices

Integrated re-combiner for electroosmotic pumps using porous frits

Using external radiators with electroosmotic pumps for cooling integrated circuits

Differential planarization

RAMANATHAN SHRIRAM

Three-dimensional stacked substrate arrangements

Three-dimensional stacked substrate arrangements