Inventor
LIST R SCOTT
US40 patents
⚠️ This page may combine multiple inventors who share the name “LIST R SCOTT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
39 patentsUS7157787B2Jan 2, 2007
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
INTEL CORP867 citations99
US7056807B2Jun 6, 2006
Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
INTEL CORP245 citations99
US7037804B2May 2, 2006
Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration
INTEL CORP258 citations99
US6975016B2Dec 13, 2005
Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
INTEL CORP252 citations99
US6908565B2Jun 21, 2005
Etch thinning techniques for wafer-to-wafer vertical stacks
INTEL CORP251 citations99
US6887769B2May 3, 2005
Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
INTEL CORP516 citations99
US6790748B2Sep 14, 2004
Thinning techniques for wafer-to-wafer vertical stacks
INTEL CORP242 citations99
US6762076B2Jul 13, 2004
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
INTEL CORP579 citations99
US6661085B2Dec 9, 2003
Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
INTEL CORP536 citations99
US7615462B2Nov 10, 2009
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
INTEL CORP154 citations98
US7056813B2Jun 6, 2006
Methods of forming backside connections on a wafer stack
INTEL CORP77 citations98
US6897125B2May 24, 2005
Methods of forming backside connections on a wafer stack
INTEL CORP95 citations98
US7148565B2Dec 12, 2006
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
INTEL CORP61 citations95
US6645832B2Nov 11, 2003
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
INTEL CORP67 citations95
US6977435B2Dec 20, 2005
Thick metal layer integrated process flow to improve power delivery and mechanical buffering
INTEL CORP82 citations94
US7696015B2Apr 13, 2010
Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips
INTEL CORP15 citations93
US7105382B2Sep 12, 2006
Self-aligned electrodes contained within the trenches of an electroosmotic pump
INTEL CORP20 citations93
US7355277B2Apr 8, 2008
Apparatus and method integrating an electro-osmotic pump and microchannel assembly into a die package
INTEL CORP30 citations92
US7227257B2Jun 5, 2007
Cooling micro-channels
INTEL CORP17 citations92
US7129172B2Oct 31, 2006
Bonded wafer processing method
INTEL CORP45 citations92
US6992381B2Jan 31, 2006
Using external radiators with electroosmotic pumps for cooling integrated circuits
INTEL CORP16 citations92
US6870270B2Mar 22, 2005
Method and structure for interfacing electronic devices
INTEL CORP25 citations92
US6981849B2Jan 3, 2006
Electro-osmotic pumps and micro-channels
INTEL CORP20 citations91
US7569426B2Aug 4, 2009
Apparatus and method integrating an electro-osmotic pump and microchannel assembly into a die package
INTEL CORP14 citations84
US7034394B2Apr 25, 2006
Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same
INTEL CORP12 citations84
US6861274B2Mar 1, 2005
Method of making a SDI electroosmotic pump using nanoporous dielectric frit
INTEL CORP13 citations84
US7842553B2Nov 30, 2010
Cooling micro-channels
INTEL CORP6 citations74
US7084495B2Aug 1, 2006
Electroosmotic pumps using porous frits for cooling integrated circuit stacks
INTEL CORP7 citations74
US6664168B1Dec 16, 2003
Method of making an on-die decoupling capacitor for a semiconductor device
INTEL CORP12 citations74
US6833321B2Dec 21, 2004
Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability
INTEL CORP10 citations73
US7537954B2May 26, 2009
Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same
INTEL CORP4 citations63
US7274106B2Sep 25, 2007
Packaged electroosmotic pumps using porous frits for cooling integrated circuits
INTEL CORP2 citations63
US6790780B2Sep 14, 2004
Fabrication of 3-D capacitor with dual damascene process
INTEL CORP4 citations63
US7348217B2Mar 25, 2008
Method and structure for interfacing electronic devices
INTEL CORP2 citations62
US7723208B2May 25, 2010
Integrated re-combiner for electroosmotic pumps using porous frits
INTEL CORP0 citations52
US7667319B2Feb 23, 2010
Electroosmotic pump using nanoporous dielectric frit
INTEL CORP1 citations52
US7576432B2Aug 18, 2009
Using external radiators with electroosmotic pumps for cooling integrated circuits
INTEL CORP1 citations52
US7300871B2Nov 27, 2007
Method of doping a conductive layer near a via
INTEL CORP1 citations52
US7120817B2Oct 10, 2006
Method of signal distribution based on a standing wave within a closed loop path
INTEL CORP0 citations50