Inventor

VAJANA BRUNO

IT42 patents

⚠️ This page may combine multiple inventors who share the name “VAJANA BRUNO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAJANA BRUNO

ST MICROELECTRONICS SRL

Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions

Anti-deciphering contacts

Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions

Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions

Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions

Memory cell of the EEPROM type having its threshold set by implantation, and fabrication method

Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions

EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process

Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors

Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process

Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication

Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained

Method for obtaining a multi-level ROM in an EEPROM process flow

Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell

Simplified DSCP process for manufacturing FLOTOX EEPROM non-autoaligned semiconductor memory cells

Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions

Process for manufacturing memory cells with dimensional control of the floating gate regions

Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks

Process for the manufacturing of an electrically programmable non-volatile memory device

High efficiency memory device

Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions

Process for manufacturing nonvolatile memory cells with dimensional control of the floating gate regions

Memory cell of the EEPROM type having its threshold adjusted by implantation, and fabrication method

Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips

Process for manufacturing an electronic device including MOS transistors with salicided junctions and non-salicided resistors

Method of making high-voltage HV transistors with drain extension in a CMOS process of the dual gate type with silicide

Method for forming a muti-level ROM memory in a dual gate CMOS process, and corresponding ROM memory cell

Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information

Process for the manufacturing of an electrically programmable non-volatile memory device

Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells

SGS THOMSON MICROELECTRONICS

Bipolar transistor compatible with CMOS processes

Memory cell for EEPROM devices, and corresponding fabricating process

Process for fabricating memory cells with two levels of polysilicon for devices of EEPROM type

Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells

Method for adjusting the threshold of a read-only memory to achieve low capacitance and high breakdown voltage

High-voltage N-channel MOS transistor and associated manufacturing process

Memory cell for EEPROM devices and corresponding fabricating process

Memory cell for EEPROM devices, and corresponding fabricating process

Monolithically integrated generator of a plurality of voltage values

Memory cell for EEPROM devices, and corresponding fabricating process

ST MICROELECTRICS SRL

Rom cell with reduced drain capacitance

Process for manufacturing a ROM cell with low drain capacitance