Inventor

MARKSTEIN PETER

US12 patents

⚠️ This page may combine multiple inventors who share the name “MARKSTEIN PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INST THE DEV OF EMERGING ARCHI

5 patents

US6151669ANov 21, 2000

Methods and apparatus for efficient control of floating-point status register

INST THE DEV OF EMERGING ARCHI122 citations97

US6301705B1Oct 9, 2001

System and method for deferring exceptions generated during speculative execution

INST THE DEV OF EMERGING ARCHI59 citations96

US6578059B1Jun 10, 2003

Methods and apparatus for controlling exponent range in floating-point calculations

INST THE DEV OF EMERGING ARCHI20 citations92

US6370639B1Apr 9, 2002

Processor architecture having two or more floating-point status fields

INST THE DEV OF EMERGING ARCHI23 citations92

US6212539B1Apr 3, 2001

Methods and apparatus for handling and storing bi-endian words in a floating-point processor

INST THE DEV OF EMERGING ARCHI13 citations73

HEWLETT PACKARD CO

4 patents

US5515308AMay 7, 1996

Floating point arithmetic unit using modified Newton-Raphson technique for division and square root

HEWLETT PACKARD CO86 citations95

US5341321AAug 23, 1994

Floating point arithmetic unit using modified Newton-Raphson technique for division and square root

HEWLETT PACKARD CO78 citations95

US5671170ASep 23, 1997

Method and apparatus for correctly rounding results of division and square root computations

HEWLETT PACKARD CO53 citations92

US5631859AMay 20, 1997

Floating point arithmetic unit having logic for quad precision arithmetic

HEWLETT PACKARD CO79 citations92

HEWLETT PACKARD DEVELOPMENT CO

3 patents

US7065757B2Jun 20, 2006

MARKSTEIN PETER

INST THE DEV OF EMERGING ARCHI

Methods and apparatus for efficient control of floating-point status register

System and method for deferring exceptions generated during speculative execution

Methods and apparatus for controlling exponent range in floating-point calculations

Processor architecture having two or more floating-point status fields

Methods and apparatus for handling and storing bi-endian words in a floating-point processor

HEWLETT PACKARD CO

Floating point arithmetic unit using modified Newton-Raphson technique for division and square root

Floating point arithmetic unit using modified Newton-Raphson technique for division and square root

Method and apparatus for correctly rounding results of division and square root computations

Floating point arithmetic unit having logic for quad precision arithmetic

HEWLETT PACKARD DEVELOPMENT CO

Efficient compilation of family of related functions

Method and system for determining the correct rounding of a function

Optimize code for a family of related functions