Inventor

FOREMAN ERIC A

US82 patents

⚠️ This page may combine multiple inventors who share the name “FOREMAN ERIC A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FOREMAN ERIC A

IBM

Method and system for evaluating timing in an integrated circuit

Method and system for evaluating timing in an integrated circuit

IC chip at-functional-speed testing with process coverage evaluation

Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis

Slack sensitivity to parameter variation based timing analysis

Prioritizing of nets for coupled noise analysis

Voltage and frequency balancing at nominal point

Voltage and frequency balancing at nominal point

Timing optimization driven by statistical sensitivites

Dynamic voltage frequency scaling

Variable accuracy parameter modeling in statistical timing

System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time

Modeling multi-patterning variability with statistical timing

Systems and methods for correlated parameters in statistical static timing analysis

Hierarchical design of integrated circuits with multi-patterning requirements

Reducing runtime and memory requirements of static timing analysis

Systems and methods for correlated parameters in statistical static timing analysis

Parasitic extraction in an integrated circuit with multi-patterning requirements

Frequency selection with selective voltage binning

Methods for identifying failing timing requirements in a digital design

Slack sensitivity to parameter variation based timing analysis

Variable threshold system and method for multi-corner static timing analysis

Methods for practical worst test definition and debug during block based statistical static timing analysis

Estimation of process variation impact of slack in multi-corner path-based static timing analysis

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Emergency responsive navigation

Multi-sided variations for creating integrated circuits

Voltage and frequency balancing at nominal point

Voltage and frequency balancing at nominal point

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Balancing sensitivities with respect to timing closure for integrated circuits

Selective voltage binning within a three-dimensional integrated chip stack

Modeling multi-patterning variability with statistical timing

Slack sensitivity to parameter variation based timing analysis

GLOBALFOUNDRIES INC

Controlling right-of-way for priority vehicles

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

Integrated circuit chip design methods and systems using process window-aware timing analysis

Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling

FOREMAN ERIC A

Systems and methods for correlated parameters in statistical static timing analysis

System and method for common history pessimism relief during static timing analysis

Device history based delay variation adjustment during static timing analysis

BUCK NATHAN C

Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

Timing closure on multiple selective corners in a single statistical timing run

Method for modeling variation in a feedback loop of a phase-locked loop

BICKFORD JEANNE P

Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures

Adaptive power control using timing canonicals

BUCK NATHAN

Chip design and fabrication method optimized for profit

Statistical clock cycle computation

DUBUQUE JOHN P

Statistical single library including on chip variation for rapid timing and power analysis

SINHA DEBJIT

Method of performing timing analysis on integrated circuit chips with consideration of process variations