Inventor

HABITZ PETER A

US78 patents

⚠️ This page may combine multiple inventors who share the name “HABITZ PETER A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HABITZ PETER A

IBM

Method and system for evaluating timing in an integrated circuit

Method and apparatus for modeling capacitance in an integrated circuit

Method and system for evaluating timing in an integrated circuit

Electromigration check of signal nets using net capacitance to evaluate thermal characteristics

Systems and methods for single cell product path delay analysis

IC chip at-functional-speed testing with process coverage evaluation

Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis

Slack sensitivity to parameter variation based timing analysis

Prioritizing of nets for coupled noise analysis

Simplified tiling pattern method

Method of integrated circuit design by selection of noise tolerant gates

Method of calculating 3-dimensional fringe characteristics using specially formed extension shapes

Decoupled capacitance calculator for orthogonal wiring patterns

Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing

Modeling multi-patterning variability with statistical timing

Systems and methods for correlated parameters in statistical static timing analysis

Hierarchical design of integrated circuits with multi-patterning requirements

Systems and methods for correlated parameters in statistical static timing analysis

Parasitic extraction in an integrated circuit with multi-patterning requirements

Methods for identifying failing timing requirements in a digital design

System and method for generating at-speed structural tests to improve process and environmental parameter space coverage

Slack sensitivity to parameter variation based timing analysis

Variable threshold system and method for multi-corner static timing analysis

Method and structure for chip-level testing of wire delay independent of silicon delay

Method of generating wiring routes with matching delay in the presence of process variation

Estimation of process variation impact of slack in multi-corner path-based static timing analysis

Forming statistical model of independently variable parameters for timing analysis

Method of generating wiring routes with matching delay in the presence of process variation

Ring oscillator structure and method of separating random and systematic tolerance values

Method for use of hierarchy in extraction

Modeling multi-patterning variability with statistical timing

Slack sensitivity to parameter variation based timing analysis

Balanced accuracy for extraction

BICKFORD JEANNE P

Test path selection and test program generation for performance testing integrated circuit chips

System yield optimization using the results of integrated circuit chip performance path testing

Adaptive power control using timing canonicals

Integrated circuit product yield optimization using the results of performance path testing

Method and system to predict a number of electromigration critical elements

BUCK NATHAN C

Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

Timing closure on multiple selective corners in a single statistical timing run

Method for modeling variation in a feedback loop of a phase-locked loop

Integrating manufacturing feedback into integrated circuit structure design

FOREMAN ERIC A

Systems and methods for correlated parameters in statistical static timing analysis

System and method for common history pessimism relief during static timing analysis

Device history based delay variation adjustment during static timing analysis

BUCK NATHAN

Chip design and fabrication method optimized for profit

Statistical clock cycle computation

DUBUQUE JOHN P

Statistical single library including on chip variation for rapid timing and power analysis

AGARWAL KANAK B

Parallel array architecture for constant current electro-migration stress testing

SINHA DEBJIT

Method of performing timing analysis on integrated circuit chips with consideration of process variations