Inventor

OKUNO YASUTOSHI

JP121 patents

⚠️ This page may combine multiple inventors who share the name “OKUNO YASUTOSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OKUNO YASUTOSHI

TAIWAN SEMICONDUCTOR MFG CO LTD

Memory cell and method of manufacturing the same

Interconnect structures and methods of forming the same

Semiconductor device with source/drain contact formed using bottom-up deposition

Selective dual silicide formation

Field effect transistors with dual silicide contact structures

Memory array circuit and method of manufacturing same

Memory array circuit and method of manufacturing same

Semiconductor device

Interface profile control in epitaxial structures for semiconductor devices

Contact structures with deposited silicide layers

Selective dual silicide formation using a maskless fabrication process flow

Selective high-K formation in gate-last process

Method of forming contact plugs for semiconductor device

Method of fabricating gate oxide of semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor device, interconnection structure and method for forming the same

Multi-layer semiconductor device structure

Semiconductor structure with enhanced contact and method of manufacture the same

Semiconductor device including fin structure with two channel layers and manufacturing method thereof

Selective dual silicide formation

Field effect transistors with dual silicide contact structures

Selective dual silicide formation

Methods for probing semiconductor fins through four-point probe and determining carrier concentrations

Memory array circuit and method of manufacturing same

Semiconductor device having spacer residue

Semiconductor device and method

TEXAS INSTRUMENTS INC

Silicon oxide germanium resonant tunneling

Method of forming multiple gate oxide thicknesses using high density plasma nitridation

Method for manufacturing dielectric capacitor, dielectric memory device

Silicon oxide germanium resonant tunneling

Structure and method for a large-permittivity dielectric using a germanium layer

Semiconductor device having a multilayer wiring and the method for fabricating the device

Integrated dielectric and method

Structure and method for a large-permittivity gate using a germanium layer

Hexagonally symmetric integrated circuit cell

Shallow trench isolation formation with sidewall spacer

MATSUSHITA ELECTRIC INDUSTRIAL CO LTD

Semiconductor memory device and method for fabricating the same

Semiconductor device and method of fabricating the same

Semiconductor integrated circuit device

Method for manufacturing semiconductor device

Semiconductor device and method for fabricating the same

Method for fabricating semiconductor device

Resistance defect assessment device, resistance defect assessment method, and method for manufacturing resistance defect assessment device

TAIWAN SEMICONDUCTOR MFG

Multi-layer semiconductor device structure

Calculating carrier concentrations in semiconductor Fins using probed resistance

FinFET with metal gate stressor

LIU KUAN-TING

Multi-layer scavenging metal gate stack for ultra-thin interfacial dielectric layer

KELLY ANDREW JOSEPH

FinFET with metal gate stressor

MATSUSHITA ELECTRONICS CORP

Method for fabricating a semiconductor device

WANN CLEMENT HSINGJEN

Semiconductor device and method of forming the same