Inventor

VENTRONE SEBASTIAN T

US185 patents

⚠️ This page may combine multiple inventors who share the name “VENTRONE SEBASTIAN T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VENTRONE SEBASTIAN T

IBM

Method for designing an integrated circuit having multiple voltage domains

Simulation based power optimization

Apparatus and method for efficient battery utilization in portable personal computers

System and method for planning a design project, coordinating project resources and tools and monitoring project progress

Method and apparatus for controlling common-mode output voltage in fully differential amplifiers

Performance based system and method for dynamic allocation of a unified multiport cache

System and method for balancing delay of signal communication paths through well voltage adjustment

Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

Programmable capacitors and methods of using the same

System and method for inserting leakage reduction control in logic circuits

Design structures, method and systems of powering on integrated circuit

Dynamic object-level code transaction for improved performance of a computer

Test system for integrated circuits

Digital reliability monitor having autonomic repair and notification capability

In-line code suppression

Voltage island fencing

Logic power optimization algorithm

System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology

Method and apparatus for preventing thermal failure in a semiconductor device through redundancy

Control of multiple equivalent functional units for power reduction

Low power LSSD flip flops and a flushable single clock splitter for flip flops

Virtual cache registers with selectable width for accommodating different precision data formats

Toggle based application specific core methodology

Integrated hot spot detector for design, analysis, and control

System and method for correcting timing signals in integrated circuits

Method and circuit for providing copy protection in an application-specific integrated circuit

Method and circuit for providing copy protection in an application-specific integrated circuit

Device and method to reduce power consumption in integrated semiconductor devices using a low power groggy mode

Method for modifying the behavior of a state machine

Configurable real prototype hardware using cores and memory macros

Method and apparatus for reducing power consumption in VLSI circuit designs

Soft fuses using bist for cache self test

Asynchronous clock switching between first and second clocks by extending phase of current clock and switching after a predetermined time and appropriated transitions

RISC-type pipeline processor having N slower execution units operating in parallel interleaved and phase offset manner with a faster fetch unit and a faster decoder

System and method for allocating memory allocation bandwidth by assigning fixed priority of access to DMA machines and programmable priority to processing unit

System and method for fencing any one of the plurality of voltage islands using a lookup table including AC and DC components for each functional block of the voltage islands

Cooling apparatus for an integrated circuit

Automated integrated circuit design documentation

Structure for intrinsic RC power distribution for noise filtering of analog supplies

Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly

System for method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly

Design structures of powering on integrated circuit

System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA

Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Flexible multimode logic element for use in a configurable mixed-logic signal distribution path

Flexible multimode logic element for use in a configurable mixed-logic signal distribution path

GLOBALFOUNDRIES INC

Memory having thermoelectric heat pump and related IC chip package and method

Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias

PHAM DAC C

Logic macro and protocol for reduced power consumption during idle state

ARSOVSKI IGOR

Adaptive noise suppression using a noise look-up table