P

Inventor

DIEFFENDERFER JAMES N

US25 patents
⚠️ This page may combine multiple inventors who share the name “DIEFFENDERFER JAMES N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

24 patents
US5996092ANov 30, 1999

System and method for tracing program execution within a processor before and after a triggering event

IBM127 citations98
US6826747B1Nov 30, 2004

System and method for tracing program instructions before and after a trace triggering event within a processor

IBM88 citations97
US5224213AJun 29, 1993

Ping-pong data buffer for transferring data from one data bus to another data bus

IBM133 citations97
US5884051AMar 16, 1999

System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities

IBM61 citations95
US5910930AJun 8, 1999

Dynamic control of power management circuitry

IBM92 citations94
US5809293ASep 15, 1998

System and method for program execution tracing within an integrated processor

IBM58 citations94
US5724572AMar 3, 1998

Method and apparatus for processing null terminated character strings

IBM27 citations92
US7730282B2Jun 1, 2010

Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector

IBM20 citations87
US5926831AJul 20, 1999

Methods and apparatus for control of speculative memory accesses

IBM18 citations84
US5734600AMar 31, 1998

Polynomial multiplier apparatus and method

IBM19 citations83
US6970962B2Nov 29, 2005

Transfer request pipeline throttling

IBM13 citations82
US7281120B2Oct 9, 2007

Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor

IBM11 citations81
US7089376B2Aug 8, 2006

Reducing snoop response time for snoopers without copies of requested data via snoop filtering

IBM8 citations72
US6976132B2Dec 13, 2005

Reducing latency of a snoop tenure

IBM8 citations72
US7093058B2Aug 15, 2006

Single request data transfer regardless of size and alignment

IBM6 citations70
US5590372ADec 31, 1996

VME bus transferring system broadcasting modifiers to multiple devices and the multiple devices simultaneously receiving data synchronously to the modifiers without acknowledging the modifiers

IBM16 citations70
US5333301AJul 26, 1994

Data transfer bus system and method serving multiple parallel asynchronous units

IBM14 citations69
US7395372B2Jul 1, 2008

Method and system for providing cache set selection which is power optimized

IBM6 citations61
US7319578B2Jan 15, 2008

Digital power monitor and adaptive self-tuning power management

IBM2 citations59
US7685373B2Mar 23, 2010

Selective snooping by snoop masters to locate updated data

IBM0 citations51
US7395380B2Jul 1, 2008

Selective snooping by snoop masters to locate updated data

IBM0 citations51
US7711930B2May 4, 2010

Apparatus and method for decreasing the latency between instruction cache and a pipeline processor

IBM1 citations49
US6993619B2Jan 31, 2006

Single request data transfer regardless of size and alignment

IBM1 citations48
US7321954B2Jan 22, 2008

Method for software controllable dynamically lockable cache line replacement system

IBM1 citations47

QUALCOMM INC

1 patent