Inventor

KENGERI SUBRAMANI

US48 patents

⚠️ This page may combine multiple inventors who share the name “KENGERI SUBRAMANI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KENGERI SUBRAMANI

ALLIANCE SEMICONDUCTOR CORP

Interleaved stitch using segmented word lines

Highly integrated low voltage SRAM array with low resistance Vss lines

Staggered pipeline access scheme for synchronous random access memory

Random access memory with fast, compact sensing and selection architecture

Fast redundancy scheme for high density, high speed memories

Apparatus and method of reducing the pre-charge time of bit lines in a random access memory

High performance random access memory with multiple local I/O lines

Staggered pipeline access scheme for synchronous random access memory

RASHED MAHBUB

Semiconductor device with transistor local interconnects

Semiconductor device with transistor local interconnects

Methods of using a trench salicide routing layer

Middle-of-the-line constructs using diffusion contact structures

Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same

Providing timing-closed FinFET designs from planar designs

SILICON ACCESS NETWORKS INC

Structure and method of an encoded ternary content addressable memory (CAM) cell for low-power compare operation

DRAM based refresh-free ternary CAM

Pseudo dual-port DRAM for simultaneous read/write access

Charge shared match line differential generation for CAM

Read zero DRAM

TAIWAN SEMICONDUCTOR MFG

Write assist circuit for improving write margins of SRAM cells

WAK devices in SRAM cells for improving VCCMIN

SRAM device with a power saving module controlled by word line signals

No-disturb bit line write for improving speed of eDRAM

SILICON ACCESS NETWORKS

2T dual-port DRAM in a pure logic process with non-destructive read capability

Loadless NMOS four transistor SRAM cell

Compact load-less static ternary CAM

HSU KUOYUAN

Memory circuits, systems, and method of interleaving accesses thereof

Measuring electrical resistance

Memory circuits, systems, and method of interleavng accesses thereof

KENGERI SUBRAMANI

Memory building blocks and memory design using automatic design tools

Memory building blocks and memory design using automatic design tools

No-disturb bit line write for improving speed of eDRAM

ALLIANCE SEMICONDUCTOR

High performance multi-bank compact synchronous DRAM architecture

Split-bank architecture for high performance SDRAMs

TEXAS INSTRUMENTS INC

Apparatus and method for power reduction in dRAM units

High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage

VIRAGE LOGIC CORP

Method and system for accelerated detection of weak bits in an SRAM memory device

Multi-port memory utilizing an array of single-port memory cells

GLOBALFOUNDRIES US INC

Semiconductor device with transistor local interconnects

Semiconductor device with transistor local interconnects

GLOBALFOUNDRIES INC

Semiconductor device with transistor local interconnects

Middle-of-the-line constructs using diffusion contact structures

ALTERA CORP

Error checking and correcting for content addressable memories (CAMs)

APPLIED MATERIALS INC

Method and system for intelligent selectivity of material application

TARABBIA MARC

Semiconductor device having contact layer providing electrical connections

TAIWAN SEMICONDUCTOR MFG CO LTD

Circuit having capacitor coupled with memory element

TAIWAN SEMICONDUCTOR MANFACTURING COMPANY LTD

Measuring electrical resistance

SHAW CHING-HAO

Providing capacitors to improve radiation hardening in memory elements