Inventor

LINDE REED

US11 patents

⚠️ This page may combine multiple inventors who share the name “LINDE REED”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OPTIMAL PLUS LTD

3 patents

US9529036B2Dec 27, 2016

Systems and methods for test time outlier detection and correction in integrated circuit testing

OPTIMAL PLUS LTD4 citations82

US11919046B2Mar 5, 2024

System and method for binning at final test

OPTIMAL PLUS LTD0 citations54

US11235355B2Feb 1, 2022

System and method for binning at final test

OPTIMAL PLUS LTD0 citations54

OPTIMALTEST LTD

2 patents

US7969174B2Jun 28, 2011

Systems and methods for test time outlier detection and correction in integrated circuit testing

OPTIMALTEST LTD13 citations90

US8872538B2Oct 28, 2014

Systems and methods for test time outlier detection and correction in integrated circuit testing

OPTIMALTEST LTD0 citations50

LINDE REED

2 patents

US10118200B2Nov 6, 2018

System and method for binning at final test

LINDE REED3 citations69

US8838408B2Sep 16, 2014

Misalignment indication decision system and method

LINDE REED2 citations53

INTEL CORP

1 patent

US7405586B2Jul 29, 2008

Ultra low pin count interface for die testing

INTEL CORP17 citations82

OPTIMAL TEST LTD

1 patent

US7528622B2May 5, 2009

Methods for slow test time detection of an integrated circuit during parallel testing

OPTIMAL TEST LTD8 citations78

BALOG GIL

1 patent

US8421494B2Apr 16, 2013

Systems and methods for test time outlier detection and correction in integrated circuit testing

BALOG GIL3 citations59

GUROV LEONID

1 patent

US8781773B2Jul 15, 2014

System and methods for parametric testing

GUROV LEONID1 citations46