Inventor
NEQUIST ERIC
US28 patents
⚠️ This page may combine multiple inventors who share the name “NEQUIST ERIC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
19 patentsUS7861203B2Dec 28, 2010
Method and system for model-based routing of an integrated circuit
CADENCE DESIGN SYSTEMS INC16 citations92
US7725845B1May 25, 2010
System and method for layout optimization using model-based verification
CADENCE DESIGN SYSTEMS INC26 citations92
US7461359B1Dec 2, 2008
Method and mechanism for determining shape connectivity
CADENCE DESIGN SYSTEMS INC17 citations92
US7100128B1Aug 29, 2006
Zone tree method and mechanism
CADENCE DESIGN SYSTEMS INC23 citations92
US6983440B1Jan 3, 2006
Shape abstraction mechanism
CADENCE DESIGN SYSTEMS INC23 citations92
US6981235B1Dec 27, 2005
Nearest neighbor mechanism
CADENCE DESIGN SYSTEMS INC23 citations92
US7665045B1Feb 16, 2010
Method and mechanism for identifying and tracking shape connectivity
CADENCE DESIGN SYSTEMS INC10 citations84
US7721235B1May 18, 2010
Method and system for implementing edge optimization on an integrated circuit design
CADENCE DESIGN SYSTEMS INC8 citations83
US7657860B1Feb 2, 2010
Method and system for implementing routing refinement and timing convergence
CADENCE DESIGN SYSTEMS INC15 citations83
US7590955B1Sep 15, 2009
Method and system for implementing layout, placement, and routing with merged shapes
CADENCE DESIGN SYSTEMS INC8 citations83
US7100129B1Aug 29, 2006
Hierarchical gcell method and mechanism
CADENCE DESIGN SYSTEMS INC14 citations83
US8010917B2Aug 30, 2011
Method and system for implementing efficient locking to facilitate parallel processing of IC designs
CADENCE DESIGN SYSTEMS INC6 citations74
US7614028B1Nov 3, 2009
Representation, configuration, and reconfiguration of routing method and system
CADENCE DESIGN SYSTEMS INC7 citations73
US7904862B2Mar 8, 2011
Method and mechanism for performing clearance-based zoning
CADENCE DESIGN SYSTEMS INC4 citations63
US7971173B1Jun 28, 2011
Method and system for implementing partial reconfiguration and rip-up of routing
CADENCE DESIGN SYSTEMS INC3 citations62
US7698666B2Apr 13, 2010
Method and system for model-based design and layout of an integrated circuit
CADENCE DESIGN SYSTEMS INC5 citations62
US8375342B1Feb 12, 2013
Method and mechanism for implementing extraction for an integrated circuit design
CADENCE DESIGN SYSTEMS INC1 citations60
US7870517B1Jan 11, 2011
Method and mechanism for implementing extraction for an integrated circuit design
CADENCE DESIGN SYSTEMS INC3 citations60
US8386975B2Feb 26, 2013
Method, system, and computer program product for improved electrical analysis
CADENCE DESIGN SYSTEMS INC2 citations58
NEQUIST ERIC
5 patentsUS8136060B1Mar 13, 2012
Method and mechanism for identifying and tracking shape connectivity
NEQUIST ERIC5 citations73
US8069426B2Nov 29, 2011
Method and mechanism for identifying and tracking shape connectivity
NEQUIST ERIC6 citations73
US8631363B2Jan 14, 2014
Method and mechanism for identifying and tracking shape connectivity
NEQUIST ERIC1 citations62
US8635574B1Jan 21, 2014
Method and mechanism for implementing extraction for an integrated circuit design
NEQUIST ERIC0 citations48
US8316331B1Nov 20, 2012
Method and mechanism for implementing extraction for an integrated circuit design
NEQUIST ERIC0 citations48