P

Inventor

BU JIANKANG

US30 patents
⚠️ This page may combine multiple inventors who share the name “BU JIANKANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAT SEMICONDUCTOR CORP

18 patents
US7483310B1Jan 27, 2009

System and method for providing high endurance low cost CMOS compatible EEPROM devices

NAT SEMICONDUCTOR CORP19 citations92
US7447064B1Nov 4, 2008

System and method for providing a CMOS compatible single poly EEPROM with an NMOS program transistor

NAT SEMICONDUCTOR CORP31 citations87
US7773423B1Aug 10, 2010

Low power, CMOS compatible non-volatile memory cell and related method and memory array

NAT SEMICONDUCTOR CORP14 citations84
US7532496B1May 12, 2009

System and method for providing a low voltage low power EPROM based on gate oxide breakdown

NAT SEMICONDUCTOR CORP12 citations84
US7514940B1Apr 7, 2009

System and method for determining effective channel dimensions of metal oxide semiconductor devices

NAT SEMICONDUCTOR CORP16 citations84
US7471572B1Dec 30, 2008

System and method for enhancing erase performance in a CMOS compatible EEPROM device

NAT SEMICONDUCTOR CORP10 citations84
US8004032B1Aug 23, 2011

System and method for providing low voltage high density multi-bit storage flash memory

NAT SEMICONDUCTOR CORP10 citations81
US7804714B1Sep 28, 2010

System and method for providing an EPROM with different gate oxide thicknesses

NAT SEMICONDUCTOR CORP9 citations80
US7646638B1Jan 12, 2010

Non-volatile memory cell that inhibits over-erasure and related method and memory array

NAT SEMICONDUCTOR CORP7 citations73
US7586792B1Sep 8, 2009

System and method for providing drain avalanche hot carrier programming for non-volatile memory applications

NAT SEMICONDUCTOR CORP7 citations70
US7512499B1Mar 31, 2009

System and method for determining substrate doping density in metal oxide semiconductor devices

NAT SEMICONDUCTOR CORP3 citations59
US7910420B1Mar 22, 2011

System and method for improving CMOS compatible non volatile memory retention reliability

NAT SEMICONDUCTOR CORP3 citations58
US7781289B1Aug 24, 2010

Method for fabricating higher quality thicker gate oxide in a non-volatile memory cell and associated circuits

NAT SEMICONDUCTOR CORP0 citations50
US7777271B1Aug 17, 2010

System and method for providing low cost high endurance low voltage electrically erasable programmable read only memory

NAT SEMICONDUCTOR CORP0 citations50
US8013400B1Sep 6, 2011

Method and system for scaling channel length

NAT SEMICONDUCTOR CORP1 citations48
US7855146B1Dec 21, 2010

Photo-focus modulation method for forming transistor gates and related transistor devices

NAT SEMICONDUCTOR CORP0 citations48
US7790491B1Sep 7, 2010

Method for forming non-volatile memory cells and related apparatus and system

NAT SEMICONDUCTOR CORP0 citations48
US7838203B1Nov 23, 2010

System and method for providing process compliant layout optimization using optical proximity correction to improve CMOS compatible non volatile memory retention reliability

NAT SEMICONDUCTOR CORP0 citations46

IDEAL POWER INC

5 patents

BU JIANKANG

4 patents

BUDRI THANAS

1 patent

POWER INTEGRATIONS INC

1 patent

LABONTE ANDRE P

1 patent