Inventor · disambiguated record
Shouli Steve Hsia
Also filed as: HSIA SHOULI · HSIA SHOULI STEVE
12 granted patents·130 citations·filing 1997–2014
91Inventor score
Top patents by PatentIndex Score
12 records- 0189US8587018B2LED structure having embedded zener diodeHSIA SHOULI STEVE·Filed 2011·Granted Nov 19, 2013·11 cites·19 claims
- 0264US9184334B2LED structureTSMC SOLID STATE LIGHTING LTD·Filed 2014·Granted Nov 10, 2015·0 cites·20 claims
- 0362US8809899B2LED structureTSMC SOLID STATE LIGHTING LTD·Filed 2013·Granted Aug 19, 2014·0 cites·16 claims
- 0461US6424019B1Shallow trench isolation chemical-mechanical polishing processLSI LOGIC CORP·Filed 2000·Granted Jul 23, 2002·9 cites·4 claims
- 0560US6034401ALocal interconnection process for preventing dopant cross diffusion in shared gate electrodesLSI LOGIC CORP·Filed 1998·Granted Mar 7, 2000·22 cites·15 claims
- 0659US6495408B1Local interconnection process for preventing dopant cross diffusion in shared gate electrodesLSI LOGIC CORP·Filed 2000·Granted Dec 17, 2002·8 cites·21 claims
- 0757US6060370AMethod for shallow trench isolations with chemical-mechanical polishingLSI LOGIC CORP·Filed 1998·Granted May 9, 2000·20 cites·17 claims
- 0852US6174798B1Process for forming metal interconnect stack for integrated circuit structureLSI LOGIC CORP·Filed 1999·Granted Jan 16, 2001·15 cites·8 claims
- 0951US6087726AMetal interconnect stack for integrated circuit structureLSI LOGIC CORP·Filed 1999·Granted Jul 11, 2000·14 cites·11 claims
- 1049US6037262AProcess for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structureLSI LOGIC CORP·Filed 1998·Granted Mar 14, 2000·16 cites·23 claims
- 1140US6147409AModified multilayered metal line structure for use with tungsten-filled vias in integrated circuit structuresLSI LOGIC CORP·Filed 1998·Granted Nov 14, 2000·10 cites·5 claims
- 1236US6046113ACombined dry and wet etch for improved silicide formationTEXAS INSTRUMENTS INC·Filed 1997·Granted Apr 4, 2000·5 cites·26 claims
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