Inventor

BOSSHART PATRICK W

US98 patents

⚠️ This page may combine multiple inventors who share the name “BOSSHART PATRICK W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOSSHART PATRICK W

TEXAS INSTRUMENTS INC

Memory with storage cells having SOI drive and access transistors with tied floating body connections

Memory with storage cells having SOI drive and access transistors with tied floating body connections

Packet processing match and action unit with configurable memory allocation

Bus interface buffer control in a microprocessor

Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure

Circuit and method for translating signals between clock domains in a microprocessor

Computer system having mixed macrocode and microcode

Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s)

Differential SOI amplifiers having tied floating body connections

Circuit to improve electrostatic discharge protection

Cache memory addressable by both physical and virtual addresses

Multiple precision multiplication device

Packet processing match and action unit with a VLIW action engine

Packet processing VLIW action unit with or-multi-ported instruction memory

Processor with conditional instruction execution based upon state of corresponding annul bit of annul code

Dynamic logic circuits using transistors having differing threshold voltages and delayed low threshold voltage leakage protection

Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer

Data storage circuits using a low threshold voltage output enable circuit

Differential SOI amplifiers having tied floating body connections

Dynamic logic circuits using selected transistors connected to absolute voltages and additional selected transistors connected to selectively disabled voltages

Data storage circuits using a low threshold voltage output enable circuit

Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access

Phase-locked loop circuit with a multi-cycle phase detector and multi-current charge pump

Circuits, systems, and methods for re-mapping memory column redundancy

Dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output

Domino logic circuits, systems, and methods with precharge control based on completion of evaluation by the subsequent domino logic stage

Apparatus for caching system management memory in a computer having a system management mode employing address translation

Dynamic logic circuits using transistors having differing threshold voltages

Using cascode transistors having low threshold voltages

Power reduction circuits and systems for dynamic logic gates

Circuit and method for detecting if a sum of two multidigit numbers equals a third multidigit number prior to availability of the sum

Method and system for high-speed virtual-to-physical address translation and cache tag matching

Method of detecting arithmetic or logical computation result

Cross-coupled complementary bit lines for a semiconductor memory with pull-up circuitry

Shifter circuit for an arithmetic logic unit in a microprocessor

Memory management system for checkpointed logic simulator with increased locality of data

Logic simulator employing hierarchical checkpointing

Compound domino CMOS circuit

Packet processing match and action unit with configurable memory allocation

Openflow match and action pipeline structure

TCAM with efficient multiple dimension range search capability

Integrated circuit having efficiently packed decoupling capacitors

BAREFOOT NETWORKS INC

Hash table storing reduced search key

Runtime sharing of unit memories between match tables in a network forwarding element

Forwarding element data plane with computing parameter distributor

Forwarding element data plane with computing parameter distributor

BOSSHART PATRICK W

Low power ternary content-addressable memory (TCAM)

System and method for integrated circuit layout editing using reference frames

BHADRA SANDEEP

Method and apparatus for packet switching

(unassigned)

Computer pipeline including dual-ported, content-addressable writebuffer