Inventor

IYER RAVISHANKAR

US93 patents

⚠️ This page may combine multiple inventors who share the name “IYER RAVISHANKAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IYER RAVISHANKAR

INTEL CORP

Priority aware selective cache allocation

Graphics processor operation scheduling for deterministic latency

Multi-modal touch screen emulator

Methods and apparatuses for controlling thread contention

Methods and apparatuses for controlling thread contention

Dynamic quality of service (QoS) for a shared cache

Selective storage of data in levels of a cache memory

Selectively inclusive cache architecture

Techniques to save or delete a video clip

Techniques to dynamically allocate resources of configurable computing resources

Differentiating cache reliability to reduce minimum on-die voltage

System and method for adaptive skin tone detection

Methods and apparatuses for controlling thread contention

Methods and apparatuses for controlling thread contention

Methods and apparatuses for controlling thread contention

Sharing information between guests in a virtual machine environment

Cache sharing based thread control

Real time video summarization

Apparatus and method for a resource allocation control framework using performance markers

Apparatus and method for real time graphics processing using local and cloud-based graphics processing resources

Methods, systems, articles of manufacture and apparatus to improve autonomous machine capabilities

Systems, methods, and apparatuses for resource monitoring

Cache allocation with code and data prioritization

Cache allocation with code and data prioritization

On-demand generation and personalization of video content

Apparatus and method for real time graphics processing using local and cloud-based graphics processing resources

Power efficient processor architecture

Methods and apparatuses for controlling thread contention

Apparatus and method for heterogeneous processors mapping to virtual cores

Arbitrating memory accesses via a shared memory fabric

Hetergeneous processor apparatus and method

KENNAMETAL INC

Nonagon cutting insert

Cutting insert with finishing and roughing cutting edges

Cutting insert

Composite milling cutter

Cutting tool having insert pocket with cantilevered member

HERDRICH ANDREW

Methods and apparatuses for controlling thread contention

Methods and apparatuses for controlling thread contention

HERDRICH ANDREW J

End-to-end datacenter performance control

Power efficient processor architecture

FANG ZHEN

Control of on-die system fabric blocks

Controlling access to a cache memory using privilege level information

ZHANG YONG

Optimized fast hessian matrix computation architecture

KOVAC JEFFREY F

Cutting insert

ZHAO LI

Monitoring cache usage in a distributed shared cache

IYER RAVISHANKAR

Application scheduling in heterogeneous multiprocessor computing platform based on a ratio of predicted performance of processor cores

MOSES JAIDEEP

Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing

MAKINENI SRIHARI

Packet coalescing

CHENG LIQUN

Searching a shared cache by using search hints and masked ways

LI BIN

Efficient peer-to-peer communication support in SoC fabrics