Inventor

HALLNOR ERIK G

US8 patents

⚠️ This page may combine multiple inventors who share the name “HALLNOR ERIK G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

3 patents

US9710041B2Jul 18, 2017

Masking a power state of a core of a processor

INTEL CORP7 citations83

US9954792B2Apr 24, 2018

Shared flow control credits

INTEL CORP3 citations69

US9785223B2Oct 10, 2017

Power management in an uncore fabric

INTEL CORP0 citations46

ZHAO LI

1 patent

US8392657B2Mar 5, 2013

Monitoring cache usage in a distributed shared cache

ZHAO LI10 citations82

FANG ZHEN

1 patent

US8316184B2Nov 20, 2012

Domain-based cache management, including domain event based priority demotion

FANG ZHEN2 citations60

LIU YEN CHENG

1 patent

US10705961B2Jul 7, 2020

Scalably mechanism to implement an instruction that monitors for writes to an address

LIU YEN CHENG1 citations59

HALLNOR ERIK G

1 patent

US8090967B2Jan 3, 2012

Power state transition initiation control of memory interconnect based on early warning signal, memory response time, and wakeup delay

HALLNOR ERIK G4 citations56

ZHANG ZHONGYING

1 patent

US9336156B2May 10, 2016

Method and apparatus for cache line state update in sectored cache with line state tracker

ZHANG ZHONGYING1 citations44