Inventor

GROHOSKI GREGORY F

US49 patents

⚠️ This page may combine multiple inventors who share the name “GROHOSKI GREGORY F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GROHOSKI GREGORY F

SUN MICROSYSTEMS INC

Processor including general-purpose and cryptographic functionality in which cryptographic operations are visible to user-specified software

Apparatus and method for implementing a block cipher algorithm

Methods and systems for efficiently integrating a cryptographic co-processor

Precise error handling in a fine grain multithreaded multicore processor

Multiple-core processor with flexible mapping of processor cores to cache banks

Apparatus and method for implementing a unified hash algorithm pipeline

Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor

Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores

Apparatus and method for fine-grained multithreading in a multipipelined processor core

Hardware demapping of TLBs shared by multiple threads

Synchronization primitives for flexible scheduling of functional unit operations

Performance instrumentation in a fine grain multithreaded multicore processor

Apparatus and method for sharing a functional unit execution resource among a plurality of functional units

Real-time address trace generation

IBM

Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers

Parallel processor instruction dispatch apparatus with interrupt handler

Crossbar switch apparatus and protocol

System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor

Tightly coupled multiprocessor instruction synchronization

Single cycle dispatch delay in a multiple instruction dispatch mechanism of a data processing system

Cache performance in an information handling system employing page searching

ORACLE AMERICA INC

Enabling on-chip features via efuses

Method and apparatus for precisely identifying effective addresses associated with hardware events

Apparatus and method for implementing a hash algorithm word buffer

Apparatus and method for local operand bypassing for cryptographic instructions

Register access protocol in a multihreaded multi-core processor

Apparatus and method for cryptographic key expansion

Minimizing TLB comparison size

SAMBANOVA SYSTEMS INC

Routing circuits for defect repair for a reconfigurable data processor

Defect repair circuits for a reconfigurable data processor

Switch for routing data in an array of functional configurable units

Defect repair for a reconfigurable data processor for homogeneous subarrays

Defect avoidance in a multidimensional array of functional configurable units

Systems and methods for editing topology of a reconfigurable data processor

OLSON CHRISTOPHER H

Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithm

Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)

Apparatus and method for implementing instruction support for the camellia cipher algorithm

Instruction support for performing montgomery multiplication

GOLLA ROBERT T

Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations

Dynamic allocation of resources in a threaded, heterogeneous processor

System and method for balancing instruction loads between multiple execution units using assignment history

GROHOSKI GREGORY F

System and method to manage address translation requests

System and method to invalidate obsolete address translations

SHAH MANISH K

Return address prediction in multithreaded processors

Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor

ORACLE INT CORP

Detection of multiple accesses to a row address of a dynamic memory within a refresh period

Detection of multiple accesses to a row address of a dynamic memory within a refresh period

JORDAN PAUL J

APIC implementation for a highly-threaded x86 processor

SPRACKLEN LAWRENCE A

Methods and mechanisms to support multiple features for a number of opcodes