Inventor

JORDAN PAUL J

US35 patents

⚠️ This page may combine multiple inventors who share the name “JORDAN PAUL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JORDAN PAUL J

SUN MICROSYSTEMS INC

Methods and systems for efficiently integrating a cryptographic co-processor

Precise error handling in a fine grain multithreaded multicore processor

TLB tag parity checking without CAM read

Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores

Hardware demapping of TLBs shared by multiple threads

Performance instrumentation in a fine grain multithreaded multicore processor

Single bit control of threads in a multithreaded multicore processor

Apparatus and method for floating-point exception prediction and recovery

Efficient implementation of timers in a multithreaded processor

Minimal address state in a fine grain multithreaded processor

Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes

Real-time address trace generation

Multiple contexts for efficient use of translation lookaside buffer

Software accessible fast VA to PA translation

Arbitration of window swap operations

JORDAN PAUL J

APIC implementation for a highly-threaded x86 processor

Dynamic tag allocation in a multithreaded out-of-order processor

Register error correction of speculative data in an out-of-order processor

Register error correction of speculative data in an out-of-order processor

ORACLE AMERICA INC

Method and apparatus for precisely identifying effective addresses associated with hardware events

Delay slot handling in a processor

Minimizing TLB comparison size

GROHOSKI GREGORY F

System and method to manage address translation requests

System and method to invalidate obsolete address translations

IBM

Method and system for triggering a debugging unit

Soft error detection in high speed microprocessors

OLSON CHRISTOPHER H

Processor and method providing instruction support for instructions that utilize multiple register windows

Processor and method for implementing instruction support for multiplication of large operands

ORACLE INT CORP

Load-monitor mwait

Precise excecution of versioned store instructions

CHOU YUAN C

Branch misprediction recovery mechanism for microprocessors

SAMBANOVA SYSTEMS INC

Non-uniform memory interleave method

GOLLA ROBERT T

Processor operating mode for mitigating dependency conditions between instructions having different operand sizes

RADOVIC ZORAN

Method and apparatus for using unused bits in a memory pointer

BROOKS JEFFREY S

Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor