Inventor
MAY FRANK
DE33 patents
⚠️ This page may combine multiple inventors who share the name “MAY FRANK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
PACT XPP TECHNOLOGIES AG
11 patentsUS7266725B2Sep 4, 2007
Method for debugging reconfigurable architectures
PACT XPP TECHNOLOGIES AG59 citations98
US7210129B2Apr 24, 2007
Method for translating programs for reconfigurable architectures
PACT XPP TECHNOLOGIES AG107 citations98
US9170812B2Oct 27, 2015
Data processing system having integrated pipelined array data processor
PACT XPP TECHNOLOGIES AG67 citations97
US7657877B2Feb 2, 2010
Method for processing data
PACT XPP TECHNOLOGIES AG95 citations96
US7595659B2Sep 29, 2009
Logic cell array and bus system
PACT XPP TECHNOLOGIES AG59 citations96
US7003660B2Feb 21, 2006
Pipeline configuration unit protocols and communication
PACT XPP TECHNOLOGIES AG40 citations95
US7657861B2Feb 2, 2010
Method and device for processing data
PACT XPP TECHNOLOGIES AG20 citations92
US9047440B2Jun 2, 2015
Logical cell array and bus system
PACT XPP TECHNOLOGIES AG9 citations82
US9250908B2Feb 2, 2016
Multi-processor bus and cache interconnection system
PACT XPP TECHNOLOGIES AG4 citations72
US9141390B2Sep 22, 2015
Method of processing data with an array of data processors according to application ID
PACT XPP TECHNOLOGIES AG0 citations51
US9256575B2Feb 9, 2016
Data processor chip with flexible bus system
PACT XPP TECHNOLOGIES AG0 citations50
VORBACH MARTIN
11 patentsUS8156284B2Apr 10, 2012
Data processing method and device
VORBACH MARTIN129 citations97
US8250503B2Aug 21, 2012
Hardware definition method including determining whether to implement a function as hardware or software
VORBACH MARTIN22 citations93
US9152427B2Oct 6, 2015
Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file
VORBACH MARTIN25 citations92
US8914590B2Dec 16, 2014
Data processing method and device
VORBACH MARTIN26 citations92
US8869121B2Oct 21, 2014
Method for the translation of programs for reconfigurable architectures
VORBACH MARTIN17 citations91
US8058899B2Nov 15, 2011
Logic cell array and bus system
VORBACH MARTIN17 citations91
US8301872B2Oct 30, 2012
Pipeline configuration protocol and configuration unit communication
VORBACH MARTIN11 citations83
US8281265B2Oct 2, 2012
Method and device for processing data
VORBACH MARTIN14 citations83
US8471593B2Jun 25, 2013
Logic cell array and bus system
VORBACH MARTIN4 citations72
US7840842B2Nov 23, 2010
Method for debugging reconfigurable architectures
VORBACH MARTIN2 citations63
US8468329B2Jun 18, 2013
Pipeline configuration protocol and configuration unit communication
VORBACH MARTIN1 citations62
HYPERION CORE INC
3 patentsUS9898297B2Feb 20, 2018
Issuing instructions to multiple execution units
HYPERION CORE INC20 citations93
US10908914B2Feb 2, 2021
Issuing instructions to multiple execution units
HYPERION CORE INC11 citations85
US10409608B2Sep 10, 2019
Issuing instructions to multiple execution units
HYPERION CORE INC4 citations83
SCIENTIA SOL MENTIS AG
3 patentsUS10579584B2Mar 3, 2020
Integrated data processing core and array data processor and method for processing algorithms
SCIENTIA SOL MENTIS AG7 citations82
US10152320B2Dec 11, 2018
Method of transferring data between external devices and an array processor
SCIENTIA SOL MENTIS AG2 citations71
US10031733B2Jul 24, 2018
Method for processing data
SCIENTIA SOL MENTIS AG2 citations70