P

Inventor

OZCAN AHMET S

US76 patents
⚠️ This page may combine multiple inventors who share the name “OZCAN AHMET S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

41 patents
US8603881B1Dec 10, 2013

Raised trench metal semiconductor alloy formation

IBM19 citations92
US10269714B2Apr 23, 2019

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

IBM4 citations84
US9093425B1Jul 28, 2015

Self-aligned liner formed on metal semiconductor alloy contacts

IBM6 citations84
US8796099B2Aug 5, 2014

Inducing channel strain via encapsulated silicide formation

IBM7 citations84
US8349716B2Jan 8, 2013

Semiconductor device with reduced junction leakage and an associated method of forming such a semiconductor device

IBM7 citations84
US8030154B1Oct 4, 2011

Method for forming a protection layer over metal semiconductor contact and structure formed thereon

IBM15 citations84
US8614107B2Dec 24, 2013

Liner-free tungsten contact

IBM8 citations83
US7993987B1Aug 9, 2011

Surface cleaning using sacrificial getter layer

IBM8 citations83
US7759208B1Jul 20, 2010

Low temperature ion implantation for improved silicide contacts

IBM14 citations83
US11101219B2Aug 24, 2021

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

IBM3 citations73
US11062956B2Jul 13, 2021

Low resistance source-drain contacts using high temperature silicides

IBM1 citations73
US10985105B2Apr 20, 2021

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

IBM3 citations73
US10943988B2Mar 9, 2021

Thermally stable salicide formation for salicide first contacts

IBM1 citations73
US10937889B2Mar 2, 2021

Forming thermally stable salicide for salicide first contacts

IBM1 citations73
US10825740B2Nov 3, 2020

Low resistance source-drain contacts using high temperature silicides

IBM1 citations73
US10685888B2Jun 16, 2020

Low resistance source-drain contacts using high temperature silicides

IBM3 citations73
US10546941B2Jan 28, 2020

Forming thermally stable salicide for salicide first contacts

IBM3 citations73
US10453935B2Oct 22, 2019

Thermally stable salicide formation for salicide first contacts

IBM1 citations73
US9882005B2Jan 30, 2018

Fully depleted silicon-on-insulator device formation

IBM4 citations73
US9559202B2Jan 31, 2017

Method for forming metal semiconductor alloys in contact holes and trenches

IBM2 citations73
US10423877B2Sep 24, 2019

High memory bandwidth neuromorphic computing system

IBM3 citations72
US9786547B2Oct 10, 2017

Channel silicon germanium formation method

IBM2 citations72
US11088033B2Aug 10, 2021

Low resistance source-drain contacts using high temperature silicides

IBM0 citations63
US10930780B2Feb 23, 2021

Low parasitic capacitance and resistance finFET device

IBM0 citations63
US8021971B2Sep 20, 2011

Structure and method to form a thermally stable silicide in narrow dimension gate stacks

IBM3 citations63
US8013419B2Sep 6, 2011

Structure and method to form dual silicide e-fuse

IBM2 citations63
US12062614B2Aug 13, 2024

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

IBM0 citations62
US11862567B2Jan 2, 2024

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

IBM0 citations62
US11556343B2Jan 17, 2023

Computational method for temporal pooling and correlation

IBM0 citations62
US11100396B2Aug 24, 2021

Self-adjusting threshold for synaptic activity in neural networks

IBM0 citations62
US9230857B2Jan 5, 2016

Method to improve semiconductor surfaces and polishing

IBM2 citations59
US10546809B2Jan 28, 2020

Wafer-scale power delivery

IBM0 citations52
US10374088B2Aug 6, 2019

Low parasitic capacitance and resistance finFET device

IBM0 citations52
US10243046B2Mar 26, 2019

Fully depleted silicon-on-insulator device formation

IBM0 citations52
US10147676B1Dec 4, 2018

Wafer-scale power delivery

IBM1 citations52
US10079148B2Sep 18, 2018

Material removal process for self-aligned contacts

IBM0 citations52
US9947747B2Apr 17, 2018

Fully depleted silicon-on-insulator device formation

IBM0 citations52
US9929016B2Mar 27, 2018

Material removal process for self-aligned contacts

IBM0 citations52
US9761455B2Sep 12, 2017

Material removal process for self-aligned contacts

IBM0 citations52
US9735268B2Aug 15, 2017

Method for forming metal semiconductor alloys in contact holes and trenches

IBM0 citations52
US9553157B2Jan 24, 2017

Diffusion-controlled oxygen depletion of semiconductor contact interface

IBM0 citations52

GLOBALFOUNDRIES INC

4 patents

LAVOIE CHRISTIAN

3 patents

DE SOUZA JOEL P

1 patent

SAMSUNG ELECTRONICS CO LTD

1 patent

Showing the top 50 of 76 patents by PatentIndex Score.