Inventor
KUEHLMANN ANDREAS
US24 patents
⚠️ This page may combine multiple inventors who share the name “KUEHLMANN ANDREAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
8 patentsUS7624364B2Nov 24, 2009
Data path and placement optimization in an integrated circuit through use of sequential timing information
CADENCE DESIGN SYSTEMS INC49 citations94
US7743354B2Jun 22, 2010
Optimizing integrated circuit design through use of sequential timing information
CADENCE DESIGN SYSTEMS INC36 citations91
US7596770B1Sep 29, 2009
Temporal decomposition for design and verification
CADENCE DESIGN SYSTEMS INC20 citations91
US7559040B1Jul 7, 2009
Optimization of combinational logic synthesis through clock latency scheduling
CADENCE DESIGN SYSTEMS INC22 citations91
US7296246B1Nov 13, 2007
Multi-domain clock skew scheduling
CADENCE DESIGN SYSTEMS INC34 citations91
US7900173B1Mar 1, 2011
Temporal decomposition for design and verification
CADENCE DESIGN SYSTEMS INC7 citations83
US7913210B2Mar 22, 2011
Reducing critical cycle delay in an integrated circuit design through use of sequential slack
CADENCE DESIGN SYSTEMS INC9 citations82
US8020125B1Sep 13, 2011
System, methods and apparatus for generation of simulation stimulus
CADENCE DESIGN SYSTEMS INC10 citations76
SYNOPSYS INC
5 patentsUS9612943B2Apr 4, 2017
Prioritization of tests of computer program code
SYNOPSYS INC7 citations82
US9836390B2Dec 5, 2017
Static analysis of computer code to determine impact of change to a code component upon a dependent code component
SYNOPSYS INC7 citations81
US9032376B2May 12, 2015
Static analysis of computer code to determine impact of change to a code component upon a dependent code component
SYNOPSYS INC7 citations81
US9317399B2Apr 19, 2016
Policy evaluation based upon dynamic observation, static analysis and code change history
SYNOPSYS INC11 citations80
US10713069B2Jul 14, 2020
Software and hardware emulation system
SYNOPSYS INC1 citations58
IBM
4 patentsUS6473884B1Oct 29, 2002
Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis
IBM77 citations93
US6035107AMar 7, 2000
Method for performing functional comparison of combinational circuits
IBM86 citations93
US5629858AMay 13, 1997
CMOS transistor network to gate level model extractor for simulation, verification and test generation
IBM21 citations92
US6698003B2Feb 24, 2004
Framework for multiple-engine based verification tools for integrated circuits
IBM38 citations91
KUEHLMANN ANDREAS
4 patentsUS8418101B1Apr 9, 2013
Temporal decomposition for design and verification
KUEHLMANN ANDREAS6 citations82
US8656330B1Feb 18, 2014
Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software
KUEHLMANN ANDREAS6 citations81
US8862439B1Oct 14, 2014
General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software
KUEHLMANN ANDREAS3 citations60
US8413090B1Apr 2, 2013
Temporal decomposition for design and verification
KUEHLMANN ANDREAS1 citations60