P

Inventor

AKATSU HIROYUKI

JP48 patents
⚠️ This page may combine multiple inventors who share the name “AKATSU HIROYUKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

24 patents
US5717635AFeb 10, 1998

High density EEPROM for solid state file

IBM144 citations99
US6319794B1Nov 20, 2001

Structure and method for producing low leakage isolation devices

IBM258 citations98
US6021789AFeb 8, 2000

Wafer cleaning system with progressive megasonic wave

IBM66 citations96
US6806138B1Oct 19, 2004

Integration scheme for enhancing capacitance of trench capacitors

IBM31 citations93
US6039055AMar 21, 2000

Wafer cleaning with dissolved gas concentration control

IBM33 citations93
US6449202B1Sep 10, 2002

DRAM direct sensing scheme

IBM37 citations92
US6329704B1Dec 11, 2001

Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer

IBM34 citations92
US5932493AAug 3, 1999

Method to minimize watermarks on silicon substrates

IBM47 citations92
US7190046B2Mar 13, 2007

Bipolar transistor having reduced collector-base capacitance

IBM19 citations91
US6967136B2Nov 22, 2005

Method and structure for improved trench processing

IBM23 citations90
US6060388AMay 9, 2000

Conductors for microelectronic circuits and method of manufacture

IBM20 citations90
US7615457B2Nov 10, 2009

Method of fabricating self-aligned bipolar transistor having tapered collector

IBM9 citations84
US7425754B2Sep 16, 2008

Structure and method of self-aligned bipolar transistor having tapered collector

IBM13 citations84
US7462547B2Dec 9, 2008

Method of fabricating a bipolar transistor having reduced collector-base capacitance

IBM12 citations83
US6723611B2Apr 20, 2004

Vertical hard mask

IBM18 citations82
US6379577B2Apr 30, 2002

Hydrogen peroxide and acid etchant for a wet etch process

IBM18 citations81
US6809027B2Oct 26, 2004

Self-aligned borderless contacts

IBM12 citations74
US6806177B2Oct 19, 2004

Method of making self-aligned borderless contacts

IBM10 citations74
US6724031B1Apr 20, 2004

Method for preventing strap-to-strap punch through in vertical DRAMs

IBM12 citations74
US6387782B2May 14, 2002

Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer

IBM6 citations74
US6893938B2May 17, 2005

STI formation for vertical and planar transistors

IBM9 citations71
US6485894B1Nov 26, 2002

Method to self-align a lithographic pattern to a workpiece

IBM3 citations62
US7601646B2Oct 13, 2009

Top-oxide-early process and array top oxide planarization

IBM4 citations58
US7974866B2Jul 5, 2011

System and method for managing workflow among a plurality of business processes associated respectively with users having access rights to artifacts

IBM0 citations31

MINEBEA MITSUMI INC

8 patents

SIEMENS AG

4 patents

MINEBEA CO LTD

3 patents

INFINEON TECHNOLOGIES CORP

3 patents

AKATSU HIROYUKI

2 patents

TOSHIBA KK

1 patent

SHOWA CORP

1 patent

INFINEON TECHNOLOGIES AG

1 patent

ALPINE ELECTRONICS INC

1 patent