Inventor

PAN KUO LUNG

TW71 patents

⚠️ This page may combine multiple inventors who share the name “PAN KUO LUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAN KUO LUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Warpage control of semiconductor die package

Integrated circuit package and method

Semiconductor package and method

Chip package and method of forming the same

Integrated circuit package and method

Multi-chip semiconductor package

Chip package and method of forming the same

Warpage control of semiconductor die package

Hybrid interconnect for chip stacking

Warpage control of semiconductor die package

Chip packages and methods of manufacture thereof

Dual-sided integrated fan-out package

Semiconductor structure including a semiconductor wafer and a surface mount component overhanging a periphery of the semiconductor wafer

Package structure and method of manufacturing the same

Multi-chip semiconductor package

Integrated circuit structure and method

Chip package and method of forming the same

Chip package structure including a silicon substrate interposer and methods for forming the same

Packages with thick RDLs and thin RDLs stacked alternatingly

Integrated circuit package and method

Multi-chip semiconductor package

Package structure

Semiconductor structure including a first surface mount component and a second surface mount component and method of fabricating the semiconductor structure

Package structure and manufacturing method of package structure thereof

Package structure and method of manufacturing the same

Semiconductor package and method

Integrated circuit package and method

Dual-sided integrated fan-out package

Integrated circuit package and method of forming same

Packaging device having plural microstructures disposed proximate to die mounting region

Semiconductor device

Packaging device having plural microstructures disposed proximate to die mounting region

Semiconductor package and manufacturing method of semiconductor package

Semiconductor packages and methods of forming the same

Chip package and method of forming the same

Integrated circuit structure and method

Packages with thick RDLs and thin RDLs stacked alternatingly

Integrated fan-out packages and methods of forming the same

Semiconductor structure

Trimming and sawing processes in the formation of wafer-form packages

Integrated circuit package and method

Integrated circuit package and method

Integrated fan-out packages and methods of forming the same

Integrated circuit package and method

Method of fabricating semiconductor structure including a barrier structure in between a plurality of surface mount components and a wafer

Bonding passive devices on active dies to form 3D packages

Package structure and manufacturing method of package structure thereof

Chip package structure including a silicon substrate interposer and methods for forming the same

Methods of forming semiconductor packages

PAN KUO LUNG

Packaging methods and packaged devices