P

Inventor

MACPHERSON JOHN

US28 patents
⚠️ This page may combine multiple inventors who share the name “MACPHERSON JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CLEAR LOGIC INC

14 patents
US5885749AMar 23, 1999

Method of customizing integrated circuits by selective secondary deposition of layer interconnect material

CLEAR LOGIC INC296 citations98
US6311316B1Oct 30, 2001

Designing integrated circuit gate arrays using programmable logic device bitstreams

CLEAR LOGIC INC72 citations94
US6348742B1Feb 19, 2002

Sacrificial bond pads for laser configured integrated circuits

CLEAR LOGIC INC31 citations92
US6078091AJun 20, 2000

Inter-conductive layer fuse for integrated circuits

CLEAR LOGIC INC26 citations92
US6020648AFeb 1, 2000

Die structure using microspheres as a stress buffer for integrated circuit prototypes

CLEAR LOGIC INC17 citations92
US6060330AMay 9, 2000

Method of customizing integrated circuits by selective secondary deposition of interconnect material

CLEAR LOGIC INC17 citations84
US6096566AAug 1, 2000

Inter-conductive layer fuse for integrated circuits

CLEAR LOGIC INC14 citations73
US6087200AJul 11, 2000

Using microspheres as a stress buffer for integrated circuit prototypes

CLEAR LOGIC INC9 citations73
US5989783ANov 23, 1999

Method of customizing integrated circuits by depositing two resist layers to selectively pattern layer interconnect material

CLEAR LOGIC INC9 citations73
US5985518ANov 16, 1999

Method of customizing integrated circuits using standard masks and targeting energy beams

CLEAR LOGIC INC14 citations73
US6369437B1Apr 9, 2002

Vertical fuse structure for integrated circuits and a method of disconnecting the same

CLEAR LOGIC INC10 citations71
US5945238AAug 31, 1999

Method of making a reusable photolithography mask

CLEAR LOGIC INC15 citations71
US6239480B1May 29, 2001

Modified lead frame for improved parallelism of a die to package

CLEAR LOGIC INC7 citations69
US6235556B1May 22, 2001

Method of improving parallelism of a die to package using a modified lead frame

CLEAR LOGIC INC7 citations69

MACPHERSON JOHN

3 patents

HUBBELL LTD

3 patents

BAKER HUGHES INC

2 patents

(unassigned)

1 patent

PETER ANDREAS

1 patent

PEI JIANYONG

1 patent

INTEGRATED DEVICE TECH

1 patent

BAKER HUGHES OILFIELD OPERATIONS LLC

1 patent

SINGH GULSHAN

1 patent