Inventor

WANG LAUNG-TERNG

US39 patents

⚠️ This page may combine multiple inventors who share the name “WANG LAUNG-TERNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG LAUNG-TERNG

SYNTEST TECHNOLOGIES INC

Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Computer-aided design system to automate scan synthesis at register-transfer level

Computer-aided design system to automate scan synthesis at register-transfer level

Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuit

Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuits

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Computer-aided design system to automate scan synthesis at register-transfer level

Method and apparatus for unifying self-test with scan-test during prototype debug and production test

Multiple-capture DFT system for scan-based integrated circuits

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Method and apparatus for low-pin-count scan compression

Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Apparatus for redundancy reconfiguration of faculty memories

WANG LAUNG-TERNG

Method and apparatus for testing 3D integrated circuits

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

Multiple-capture DFT system to reduce peak capture power during self-test or scan test

Apparatus and method for protecting soft errors

Robust scan synthesis for protecting soft errors

Robust scan synthesis for protecting soft errors

Computer-aided design system to automate scan synthesis at register-transfer level

Method and apparatus for hybrid ring generator design

Multiple-capture DFT system to reduce peak capture power during self-test or scan test

SYNTEST TECH INC

Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test

Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit

TOUBA NUR A

Method and apparatus for low-pin-count scan compression

Method and apparatus for low-pin-count scan compression