Inventor
HAMILTON MICHAEL J
US31 patents
⚠️ This page may combine multiple inventors who share the name “HAMILTON MICHAEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
27 patentsUS9116205B2Aug 25, 2015
Test coverage of integrated circuits with test vector input spreading
IBM8 citations83
US9103879B2Aug 11, 2015
Test coverage of integrated circuits with test vector input spreading
IBM9 citations83
US8856720B2Oct 7, 2014
Test coverage of integrated circuits with masking pattern selection
IBM9 citations83
US8667431B1Mar 4, 2014
Test coverage of integrated circuits with masking pattern selection
IBM6 citations83
US8898530B1Nov 25, 2014
Dynamic built-in self-test system
IBM4 citations72
US10372853B2Aug 6, 2019
Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)
IBM2 citations71
US9032256B2May 12, 2015
Multi-core processor comparison encoding
IBM5 citations68
US9069041B2Jun 30, 2015
Self evaluation of system on a chip with multiple cores
IBM2 citations62
US9557383B2Jan 31, 2017
Partitioned scan chain diagnostics using multiple bypass structures and injection points
IBM0 citations52
US9551747B2Jan 24, 2017
Inserting bypass structures at tap points to reduce latch dependency during scan testing
IBM0 citations52
US9547039B2Jan 17, 2017
Inserting bypass structures at tap points to reduce latch dependency during scan testing
IBM0 citations52
US9529046B2Dec 27, 2016
Partitioned scan chain diagnostics using multiple bypass structures and injection points
IBM0 citations52
US9429622B2Aug 30, 2016
Implementing enhanced scan chain diagnostics via bypass multiplexing structure
IBM0 citations52
US9429621B2Aug 30, 2016
Implementing enhanced scan chain diagnostics via bypass multiplexing structure
IBM0 citations52
US9568549B2Feb 14, 2017
Managing redundancy repair using boundary scans
IBM0 citations51
US9201117B2Dec 1, 2015
Managing redundancy repair using boundary scans
IBM0 citations51
US9188636B2Nov 17, 2015
Self evaluation of system on a chip with multiple cores
IBM0 citations51
US9003244B2Apr 7, 2015
Dynamic built-in self-test system
IBM0 citations51
US10379159B1Aug 13, 2019
Minimization of over-masking in an on product multiple input signature register (OPMISR)
IBM0 citations50
US10345380B1Jul 9, 2019
Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading
IBM0 citations50
US9964591B2May 8, 2018
Implementing decreased scan data interdependence in on product multiple input signature register (OPMISR) through PRPG control rotation
IBM0 citations50
US7514947B2Apr 7, 2009
Method of and system for functionally testing multiple devices in parallel in a burn-in-environment
IBM0 citations45
US10060978B2Aug 28, 2018
Implementing prioritized compressed failure defects for efficient scan diagnostics
IBM0 citations41
US10371749B1Aug 6, 2019
Removal of over-masking in an on product multiple input signature register (OPMISR) test
IBM0 citations39
US10359471B2Jul 23, 2019
Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through scan skewing
IBM0 citations39
US10234507B2Mar 19, 2019
Implementing register array (RA) repair using LBIST
IBM0 citations39
US10024917B1Jul 17, 2018
Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through spreading in stumpmux daisy-chain structure
IBM0 citations39
DOUSKEY STEVEN M
3 patentsUS8516318B2Aug 20, 2013
Dynamic scan
DOUSKEY STEVEN M2 citations59
US8762803B2Jun 24, 2014
Implementing enhanced pseudo random pattern generators with hierarchical linear feedback shift registers (LFSRs)
DOUSKEY STEVEN M0 citations49
US8627162B2Jan 7, 2014
Iimplementing enhanced aperture function calibration for logic built in self test (LBIST)
DOUSKEY STEVEN M0 citations49