Inventor

BERGER NEAL

US72 patents

⚠️ This page may combine multiple inventors who share the name “BERGER NEAL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BERGER NEAL

SPIN TRANSFER TECH INC

Method and apparatus for bipolar memory write-verify

Spin transfer torque MRAM device with error buffer

Method and apparatus for bipolar memory write-verify

Perpendicular source and bit lines for an MRAM array

Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank

Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers

Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device

Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them

Memory array with individually trimmable sense amplifiers

Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers

Smart cache design to prevent overflow for a memory device with a dynamic redundancy register

ZENO SEMICONDUCTOR INC

Memory device comprising electrically floating body transistor

Memory device comprising electrically floating body transistor

Memory device comprising electrically floating body transistor

Memory device comprising electrically floating body transistor

Memory device comprising electrically floating body transistor

Memory device comprising electrically floating body transistor

Memory device comprising electrically floating body transistor

Memory device comprising electrically floating body transistor

SPIN MEMORY INC

Word line decoder memory architecture

Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments

Memory array with individually trimmable sense amplifiers

Error cache system with coarse and fine segments for power optimization

Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow

Method of optimizing write voltage based on error buffer occupancy

MRAM noise mitigation for write operations with simultaneous background operations

INTEGRATED SILICON SOLUTION CAYMAN INC

MRAM access coordination systems and methods via pipeline in parallel

Word line decoder memory architecture

MRAM access coordination systems and methods with a plurality of pipelines

Error cache system with coarse and fine segments for power optimization

Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments

Circuit engine for managing memory meta-stability

Error cache segmentation for power reduction

BERGER NEAL

MRAM-based memory device with rotated gate

Self-referenced magnetic random access memory cells

Magnetic random access memory devices configured for self-referenced read operation

Non-volatile logic devices using magnetic tunnel junctions

ATMEL CORP

Configuration control in a programmable logic device using non-volatile elements

Programmable logic device with regional and universal signal routing

Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations

EL BARAJI MOURAD

Method for writing in a MRAM-based memory device with reduced power consumption

Magnetic random access memory devices including shared heating straps

Magnetic random access memory devices including multi-bit cells

SILICON STORAGE TECH INC

Power efficient read circuit for a serial output memory device and method

Integrated circuit memory device with bit line pre-charging based upon partial address decoding

CAMBOU BERTRAND F

Apparatus, system, and method for matching patterns with an ultra fast check engine

JAVERLIAC VIRGILE

System and method for writing data to magnetoresistive random access memory cells

CROCUS TECHNOLOGY SA

Shared line magnetic random access memory cells

BARAJI MOURAD EL

Magnetic random access memory devices including heating straps