Inventor
WU NELSON
US15 patents
Patents
15 patentsUS10169186B1Jan 1, 2019
Efficient testing of direct memory address translation
IBM5 citations83
US10169185B1Jan 1, 2019
Efficient testing of direct memory address translation
IBM4 citations83
US12450411B2Oct 21, 2025
Hazard generating for speculative cores in a microprocessor
IBM0 citations62
US12130749B2Oct 29, 2024
Validation of store coherence relative to page translation invalidation
IBM0 citations62
US11620235B1Apr 4, 2023
Validation of store coherence relative to page translation invalidation
IBM0 citations62
US11094391B2Aug 17, 2021
List insertion in test segments with non-naturally aligned data boundaries
IBM0 citations62
US11061821B2Jul 13, 2021
Method, system, and apparatus for stress testing memory translation tables
IBM0 citations62
US10521355B2Dec 31, 2019
Method, system, and apparatus for stress testing memory translation tables
IBM1 citations62
US12141071B2Nov 12, 2024
Performance and reliability of processor store operation data transfers
IBM0 citations51
US12118355B2Oct 15, 2024
Cache coherence validation using delayed fulfillment of L2 requests
IBM0 citations51
US10489261B2Nov 26, 2019
Efficient testing of direct memory address translation
IBM0 citations51
US10481991B2Nov 19, 2019
Efficient testing of direct memory address translation
IBM0 citations51
US10438682B2Oct 8, 2019
List insertion in test segments with non-naturally aligned data boundaries
IBM0 citations51
US10748637B2Aug 18, 2020
System and method for testing processor errors
IBM0 citations47
US11501046B2Nov 15, 2022
Pre-silicon chip model of extracted workload inner loop instruction traces
IBM0 citations43