Inventor

BRADBURY JONATHAN D

US255 patents

⚠️ This page may combine multiple inventors who share the name “BRADBURY JONATHAN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRADBURY JONATHAN D

IBM

Fingerprint-initiated trace extraction

Vector checksum instruction

Vector checksum instruction

Cipher message with authentication instruction

Data conversion to/from selected data type with implied rounding mode

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Spilling temporary results for accommodation of memory boundaries

Increasing the scope of local purges of structures associated with address translation

Hardware transaction transient conflict resolution

Vector Galois field multiply sum and accumulate instruction

Address expansion and contraction in a multithreading computer system

Predicting the length of a transaction

Vector Galois Field Multiply Sum and Accumulate instruction

Thread context preservation in a multithreading computer system

Floating point instruction with selectable comparison attributes

Vector galois field multiply sum and accumulate instruction

Dynamic releasing of cache lines

Dynamic enablement of multithreading

Instruction to load data up to a specified memory boundary indicated by the instruction

Storage sharing between a secure domain and a non-secure entity

Secure execution guest owner environmental controls

Facilitating access to memory locality domain information

Digit validation check control in instruction execution

Secure storage query and donation

Negative zero control in instruction execution

Fracture ring sensor

Vector galois field multiply sum and accumulate instruction

Sort and merge instruction for a general-purpose processor

Electro-mechanical fuse for detecting monitored component deflection

Vector floating point test data class immediate instruction

Fracture ring sensor

Alignment based block concurrency for accessing memory

Increasing the scope of local purges of structures associated with address translation

Electro-mechanical fuse for detecting monitored component deflection

Decimal load immediate instruction

Compression hardware including active compression parameters

Perform sign operation decimal instruction

Vector Galois Field Multiply Sum and Accumulate instruction

Efficient software closing of hardware-generated encoding context

Memory preserving parse tree based compression with entropy coding

Selective purging of entries of structures associated with address translation in a virtualized environment

Mechanism for creating friendly transactions with credentials

Managing memory used to back address translation structures

Reducing over-purging of structures associated with address translation using an array of tags

Decimal shift and divide instruction

Decimal load immediate instruction

Mechanism for creating friendly transactions with credentials

Vector floating point test data class immediate instruction

BRADBURY JONATHAN D

Finding the length of a set of character data having a termination character

Character data match determination by loading registers at most up to memory block boundary and comparing