Inventor

MICHAEL MAGED M

US122 patents

⚠️ This page may combine multiple inventors who share the name “MICHAEL MAGED M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MICHAEL MAGED M

IBM

Two level virtual channels

Memory transaction having implicit ordering effects

Dynamic predictor for coalescing memory transactions

Instruction to cancel outstanding cache prefetches

Prefetching of discontiguous storage locations in anticipation of transactional execution

Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments

Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments

Salvaging hardware transactions

Dynamic predictor for coalescing memory transactions

Coalescing memory transactions

State-based allocation and replacement for improved hit ratio in directory caches

Split pending buffer with concurrent access of requests and responses to fully associative and indexed components

Complete and concise remote (CCR) directory

Hint instruction for managing transactional aborts in transactional memory computing environments

Hardware transaction transient conflict resolution

Dynamic prediction of hardware transaction resource requirements

Predicting the length of a transaction

Multi-granular cache management in multi-processor computing environments

Code optimization to enable and disable coalescing of memory transactions

Salvaging hardware transactions with instructions

Dynamic prediction of concurrent hardware transactions resource requirements and allocation

Salvaging lock elision transactions with instructions to change execution type

Salvaging lock elision transactions with instructions to change execution type

Coalescing memory transactions

Alerting hardware transactions that are about to run out of space

Code optimization to enable and disable coalescing of memory transactions

Prefetching of discontiguous storage locations as part of transactional execution

Salvaging hardware transactions with instructions

Salvaging hardware transactions

Salvaging hardware transactions

Salvaging hardware transactions with instructions

Salvaging hardware transactions

Centralized management of high-contention cache lines in multi-processor computing environments

Fault tolerant mutual exclusion locks for shared memory systems

Method for completely lock-free user-level dynamic memory allocation

Instruction to cancel outstanding cache prefetches

Interprocessor memory status communication

Instruction to cancel outstanding cache prefetches

Interprocessor memory status communication

Interprocessor memory status communication

Enabling end of transaction detection using speculative look ahead

Non-default instruction handling within transaction

Indicating nearing the completion of a transaction

Address probing for transaction

Address probing for transaction

Alerting hardware transactions that are about to run out of space

CAIN III HAROLD W

Transactional block conflict resolution based on the determination of executing threads in parallel or in serial mode

GLOBALFOUNDRIES INC

Managing high-conflict cache lines in transactional memory computing environments

MICHAEL MAGED M

Methods for single-owner multi-consumer work queues for repeatable tasks

BLUNDELL COLIN B

Atomic commit predicated on consistency of watches