Inventor
MAITREJEAN SYLVAIN
FR23 patents
⚠️ This page may combine multiple inventors who share the name “MAITREJEAN SYLVAIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
COMMISSARIAT ENERGIE ATOMIQUE
16 patentsUS10600786B2Mar 24, 2020
Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor
COMMISSARIAT ENERGIE ATOMIQUE2 citations73
US9502558B2Nov 22, 2016
Local strain generation in an SOI substrate
COMMISSARIAT ENERGIE ATOMIQUE4 citations73
US9853124B2Dec 26, 2017
Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers
COMMISSARIAT ENERGIE ATOMIQUE4 citations72
US9704709B2Jul 11, 2017
Method for causing tensile strain in a semiconductor film
COMMISSARIAT ENERGIE ATOMIQUE2 citations72
US12198940B2Jan 14, 2025
Method for modifying the strain state of a block of a semiconducting material
COMMISSARIAT ENERGIE ATOMIQUE0 citations62
US11081463B2Aug 3, 2021
Bonding method with electron-stimulated desorption
COMMISSARIAT ENERGIE ATOMIQUE0 citations62
US11688811B2Jun 27, 2023
Transistor comprising a channel placed under shear strain and fabrication process
COMMISSARIAT ENERGIE ATOMIQUE0 citations61
US10978594B2Apr 13, 2021
Transistor comprising a channel placed under shear strain and fabrication process
COMMISSARIAT ENERGIE ATOMIQUE0 citations61
US11694991B2Jul 4, 2023
Method for transferring chips
COMMISSARIAT ENERGIE ATOMIQUE1 citations59
US11195711B2Dec 7, 2021
Healing method before transfer of a semiconducting layer
COMMISSARIAT ENERGIE ATOMIQUE1 citations59
US9536951B2Jan 3, 2017
FinFET transistor comprising portions of SiGe with a crystal orientation [111]
COMMISSARIAT ENERGIE ATOMIQUE1 citations51
US11810789B2Nov 7, 2023
Method of fabricating a semiconductor substrate having a stressed semiconductor region
COMMISSARIAT ENERGIE ATOMIQUE0 citations47
US11424121B2Aug 23, 2022
Method for forming a layer by cyclic epitaxy
COMMISSARIAT ENERGIE ATOMIQUE0 citations43
US8367547B2Feb 5, 2013
Method for creating a metal crystalline region, in particular in an integrated circuit
COMMISSARIAT ENERGIE ATOMIQUE0 citations43
US10665497B2May 26, 2020
Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions
COMMISSARIAT ENERGIE ATOMIQUE0 citations41
US9853130B2Dec 26, 2017
Method of modifying the strain state of a semiconducting structure with stacked transistor channels
COMMISSARIAT ENERGIE ATOMIQUE0 citations40