Inventor

MORAND YVES

FR50 patents

⚠️ This page may combine multiple inventors who share the name “MORAND YVES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MORAND YVES

COMMISSARIAT ENERGIE ATOMIQUE

Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium

Method for producing a copper connection

Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor

Method for fabricating a structure of interconnections comprising an electric insulation including air or vacuum gaps

Method for patterning a thin film

Local strain generation in an SOI substrate

Method for producing a silicon-germanium film with variable germanium content

Contact on a heterogeneous semiconductor substrate

Method of making a semiconductor layer having at least two different thicknesses

Method of fabricating a transistor channel structure with uniaxial strain

Method for producing a component comprising at least one germanium-based element and component obtained by such a method

Fabrication of transistors having stressed channels

Forming of a MOS transistor based on a two-dimensional semiconductor material

Method for producing Si1-yGey based zones with different contents in Ge on a same substrate by condensation of germanium

Method for making a transistor of which the active region includes a semimetal material

Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location

Method for fabrication of a field-effect with reduced stray capacitance

FinFET transistor comprising portions of SiGe with a crystal orientation [111]

Nanowire and planar transistors co-integrated on utbox SOI substrate

Nanowire and planar transistors co-integrated on utbox SOI substrate

SBFET transistor and corresponding fabrication process

Transistor with MIS connections and fabricating process

Method for producing distinct first and second active semi-conducting zones and use thereof for fabricating C-MOS structures

Method of making a transistor

Method of modifying the strain state of a semiconducting structure with stacked transistor channels

Method for producing low-permittivity spacers

Method for making an integrated circuit

ST MICROELECTRONICS SA

Air-spacer MOS transistor

Process for fabricating a capacitor within an integrated circuit, and corresponding integrated circuit

High-density MOS transistor

Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material

Method for manufacturing a fin MOS transistor

Structure and method for forming conductive members in an integrated circuit

Method for manufacturing a fin MOS transistor

Method for forming a via contacting several levels of semiconductor layers

Method for forming gate, source, and drain contacts on a MOS transistor

Etching an organic material layer, particularly for producing interconnections of the damascene type

Heteroatomic single-crystal layers

COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENE ALT

Method for producing a strained semiconductor on insulator substrate

Method of making a transistor

MORAND YVES

Process for producing two interleaved patterns on a substrate

Method for manufacturing a strained channel MOS transistor

DESPLOBAIN SEBASTIEN

Method for forming a multilayer structure

ST MICROELECTRONICS

Method for making an island of material confined between electrodes, and application to transistors

HALIMAOUI AOMAR

Method for manufacturing a structure of semiconductor-on-insulator type

BENSAHEL DANIEL-CAMILLE

Method of fabricating a device with a concentration gradient and the corresponding device

VINCENT BENJAMIN

Method for preparing a germanium layer from a silicon-germanium-on-isolator substrate

ST MICROELECTRONICS CROLLES 2

Method of fabricating a device with a concentration gradient and the corresponding device

LANDIS STEFAN

Method to fabricate a mould for lithography by nano-imprinting

POIROUX THIERRY

Process for producing an integrated circuit